參數(shù)資料
型號(hào): ADC12048CIV
廠商: NATIONAL SEMICONDUCTOR CORP
元件分類: ADC
英文描述: 12-Bit Plus Sign 216 kHz 8-Channel Sampling Analog-to-Digital Converter
中文描述: 1-CH 13-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC44
封裝: PLASTIC, LCC-44
文件頁(yè)數(shù): 21/30頁(yè)
文件大?。?/td> 635K
代理商: ADC12048CIV
Typical Performance Characteristics
(See (Note 21), Electrical Characteristic Section) (Continued)
Register Bit Description
CONFIGURATION REGISTER (Write Only)
This is a 13-bit write-only register that is used to program the functionality of the ADC12048. All data written to the ADC12048 will
always go to this register only. The contents of this register cannot be read.
MSB
b
12
BW
LSB
b
11
COMMAND FIELD
b
10
b
9
b
8
b
7
HB
b
6
SE
b
5
ACQ TIME
b
4
b
3
b
2
b
1
b
0
SYNC
MUX ADDRESS
Power on State:
0100Hex
b
3
–b
0
:
The MUX ADDRESS bits configure the analog input MUX. They select which input channels of the MUX will connect to
the MUXOUT+ and MUXOUT pins. (Refer to the
MUX
section for more details on the MUX.)
Power-up
value is 0000.
TABLE 1. MUX Channel Assignment
b
3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
b
2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
b
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
b
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
MUXOUT+
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
MUXOUT
CH1
CH0
CH3
CH2
CH5
CH4
CH7
CH6
COM
COM
COM
COM
COM
COM
COM
COM
b
–b
4
:
The ACQ TIME bits select one of four possible acquistion times in SYNC-OUT mode. (Refer to
Selectable Acquisition
Time
section.)
b
5
0
0
1
1
b
4
0
1
0
1
Clocks
9
15
47
79
b
:
When the Single-Ended bit (SE bit) is set, conversion results will be limited to positive values only and any negative conver-
sion results will appear as a code of zero in the Data register. The SE bit is cleared at
power-up.
b
7
:
The High Byte bit (HB) is meaningful only in 8-bit mode (BW bit b
12
= “0”) and is a don’t care condition in 13-bit mode (BW
bit b
12
= “1”). This bit is used to access the upper byte of the Configuration Register in 8-bit mode. When this bit is set and bit
b
12
= 0, the next byte written to the ADC12048 will program the upper byte of the Configuration register. The HB bit will automati-
cally be cleared when data is written to the upper byte of the Configuration register, allowing the lower byte to be accessed with
the next write. The HB bit is cleared at
power-up.
b
:
The SYNC bit. When the SYNC bit is set, the SYNC pin is programmed as an input and the converter is in synchronous mode.
In this mode a rising edge on the SYNC pin causes the ADC to hold the input signal and begin a conversion. When b
cleared,
the SYNC pin is programmed as an output and the converter is in an asynchronous mode. In this mode the signal at the SYNC
pin indicates the status of the converter. The SYNC pin is high when a conversion is taking place. The SYNC bit is set at
power-up.
b
11
–b
9
:
The command field. These bits select the mode of operation of the ADC12048.
Power-up
value is 000. (See (Note 22))
A
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