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參數(shù)資料
| 型號： | ADC12048 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | 12-Bit Plus Sign 216 kHz 8-Channel Sampling Analog-to-Digital Converter |
| 中文描述： | 12位帶符號216 kHz的8聲道采樣模擬到數(shù)字轉(zhuǎn)換器 |
| 文件頁數(shù)： | 23/30頁 |
| 文件大?。?/td> | 635K |
| 代理商： | ADC12048 |
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Features and Operating Modes
(Continued)
being applied to the ADC inputs. The ADCIN+ and ADCIN
are the fully differential non-inverting (positive) and inverting
(negative) inputs to the analog-to-digital converter (ADC) of
the ADC12048. If no external signal conditioning is required
on the signal output of the multiplexer, MUXOUT+ should be
connected to ADCIN+ and MUXOUT should be connected
to ADCIN.
The analog input multiplexer can be set up to operate in ei-
ther one of eight differential or eight single-ended (the COM
input as the zero reference) modes. In the differential mode,
the analog inputs are paired as follows: CH0 with CH1, CH2
with CH3, CH4 with CH5 and CH6 with CH7. The input chan-
nel pairs can be connected to the MUXOUT+ and
MUXOUT pins in any order. In the single-ended mode, one
of the input channels, CH0 through CH7, can be assigned to
MUXOUT+ while the MUXOUT is always assigned to the
COM input.
STANDBY MODE
The ADC12048 has a low power consumption mode (75 μW
@
5V). This mode is entered when a Standby command is
written in the command field of the Configuration register. A
logic low appearing on the STDBY output pin indicates that
the ADC12048 is in the Standby mode. Any command other
than the Standby command written to the Configuration reg-
ister will get the ADC12048 out of the Standby mode. The
STDBY pin will immediately switch to a logic “1” as soon as
the ADC12048 is requested to get out of the standby mode.
The RDY pin will then be asserted low when the ADC is ac-
tually out of the Standby mode and ready for normal opera-
tion. The ADC12048 defaults to the Standby mode following
a hardware
power-up.
This can be verified by examining the
logic low status of the STDBY pin.
SYNC/ASYNC MODE
The ADC12048 may be programmed to operate in synchro-
nous (SYNC-IN) or asynchronous (SYNC-OUT) mode. To
enter synchronous mode, the SYNC bit in the Configuration
register must be set. TheADC12048 is in synchronous mode
after a hardware
power-up.
In this mode, the SYNC pin is
programmed as an input and conversions are synchronized
to the rising edges of the signal applied at the SYNC pin. Ac-
quisition time can also be controlled by the SYNC signal
when in synchronous mode. Refer to the sync-in timing dia-
grams. When the SYNC bit is cleared, the ADC is in asyn-
chronous mode and the SYNC pin is programmed as an out-
put. In asynchronous mode, the signal at the SYNC pin
indicates the status of the converter. This pin is high when
the converter is performing a conversion. Refer to the
sync-out timing diagrams.
SELECTABLE ACQUISITION TIME
The ADC12048’s internal sample/hold circuitry samples an
input voltage by connecting the input to an internal sampling
capacitor (approximately 70 pF) through an effective resis-
tance equal to the multiplexer “On” resistance (300
max)
plus the “On” resistance of the analog switch at the input to
the sample/hold circuit (2500
typical) and the effective out-
put resistance of the source. For conversion results to be ac-
curate, the period during which the sampling capacitor is
connected to the source (the “acquisition time”) must be long
enough to charge the capacitor to within a small fraction of
an LSB of the input voltage. An acquisition time of 750 ns is
sufficient when the external source resistance is less than
1 k
and any active or reactive source circuitry settles to
12 bits in less than 500 ns. When source resistance or
source settling time increase beyond these limits, the acqui-
sition time must also be increased to preserve precision.
In asynchronous (SYNC-OUT) mode, the acquisition time is
controlled by an internal counter. The minimum acquisition
period is 9 clock cycles, which corresponds to the nominal
value of 750 ns when the clock frequency is 12 MHz. Bits b
4
and b
of the Configuration Register are used to select the
acquisition time from among four possible values (9, 15, 47,
or 79 clock cycles). Since acquisition time in the asynchro-
nous mode is based on counting clock cycles, it is also in-
versely proportional to clock frequency:
Note that the actual acquisition time will be longer than T
ACQ
because acquisition begins either when the multiplexer
channel is changed or when RDY goes low, if the multiplexer
channel is not changed.After a read is performed, RDY goes
high, which starts the T
ACQ
counter (see Figure 9).
In synchronous (SYNC-IN) mode, bits b
and b
are ignored,
and the acquisition time depends on the sync signal applied
at the SYNC pin. If a new MUX channel is selected at the
start of the conversion, the acquisition period begins on the
active edge of the WR signal that latches in the new MUX
channel. If no new MUX channel is selected, the acquisition
period begins on the falling edge of RDY, which occurs at the
end of the previous conversion (or at the end of an autozero
or autocalibration procedure). The acquisition period ends
when SYNC goes high.
To estimate the acquisition time necessary for accurate con-
versions when the source resistance is greater than 1 k
,
use the following expression:
where R
S
is the source resistance, R
M
is the MUX “On” re-
sistance, and R
S/H
is the sample/hold “On” resistance.
If the settling time of the source is greater than 500 ns, the
acquisition time should be about 300 ns longer than the set-
tling time for a “well-behaved”, smooth settling characteristic.
FULL CALIBRATION CYCLE
A full calibration cycle compensates for the ADC’s linearity
and offset errors. The converter’s DC specifications are
guaranteed only after a full calibration has been performed.
A full calibration cycle is initated by writing a Ful-Cal com-
mand to the ADC12048. During a full calibration, the offset
error is measured eight times, averaged and a correction co-
efficient is created. The offset correction coefficient is stored
in an internal offset correction register.
The overall Iinearity correction is achieved by correctng the
internal DAC’s capacitor mismatches. Each capacitor is
compared eight times against all remaining smaller value ca-
pacitors. The errors are averaged and correction coefficients
are created.
A
www.national.com
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| ADC12048_02 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:12-Bit Plus Sign 216kHz 8-Channel Sampling Analog-to-Digital Converter |
| ADC12048CIV | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADC12048CIV/NOPB | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADC12048CIVF | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADC12048CIVF/NOPB | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 12B PLUS SIGN 216KHz 8CH SAMPLING ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
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