參數(shù)資料
型號(hào): ADC12040CIVYX
廠商: NATIONAL SEMICONDUCTOR CORP
元件分類(lèi): ADC
英文描述: 12-Bit, 40 MSPS, 340 mW A/D Converter with Internal Sample-and-Hold
中文描述: 1-CH 12-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP32
封裝: LQFP-32
文件頁(yè)數(shù): 3/20頁(yè)
文件大?。?/td> 519K
代理商: ADC12040CIVYX
Pin Descriptions and Equivalent Circuits
Pin No.
ANALOG I/O
Symbol
Equivalent Circuit
Description
2
V
IN
+
Non-Inverting analog signal Input. With a 2.0V reference
voltage, the differential input signal level is 2.0 V
P-P
centered
on V
CM
.
Inverting analog signal Input. With a 2.0V reference voltage
the input signal level is 2.0 V
P-P
centered on V
CM
. This pin
may be connected to V
CM
for single-ended operation, but a
differential input signal is required for best performance.
3
V
IN
1
V
REF
Reference input. This pin should be bypassed to AGND with
a 0.1 μF monolithic capacitor. V
REF
is 2.0V nominal and
should be between 1.0V to 2.2V.
31
V
RP
These pins are high impedance reference bypass pins only.
Connect a 0.1 μF capacitor from each of these pins to AGND.
DO NOT connect anything else to these pins.
32
V
RM
30
V
RN
DIGITAL I/O
10
CLK
Digital clock input. The range of frequencies for this input is
100 kHz to 50 MHz (typical) with guaranteed performance at
40 MHz. The input is sampled on the rising edge of this input.
11
OE
OE is the output enable pin that, when low, enables the
TRI-STATE
data output pins. When this pin is high, the
outputs are in a high impedance state.
8
PD
PD is the Power Down input pin. When high, this input puts
the converter into the power down mode. When this pin is
low, the converter is in the active mode.
A
www.national.com
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