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參數(shù)資料
| 型號： | ADC1175-50CIMT |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | ADC |
| 英文描述： | 8-Bit, 50 MSPS, 125 mW A/D Converter |
| 中文描述： | 1-CH 8-BIT RESISTANCE LADDER ADC, PARALLEL ACCESS, PDSO24 |
| 封裝： | TSSOP-24 |
| 文件頁數(shù)： | 4/17頁 |
| 文件大小： | 487K |
| 代理商： | ADC1175-50CIMT |
Absolute Maximum Ratings
(Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
AV
DD
, DV
DD
Voltage on Any Pin
V
RT
, V
RB
CLK, OE Voltage
Digital Output Voltage
Input Current (Note 3)
Package Input Current
(Note 3)
Package Dissipation at 25C
6.5V
0.3V to 6.5V
AV
SS
to AV
DD
0.05 to (AV
DD
+ 0.05V)
DV
SS
to DV
DD
±
25mA
±
50mA
(Note 4)
ESD Susceptibility (Note 5)
Human Body Model
Machine Model
Soldering Temp., Infared, 10
sec. (Note 6)
Storage Temperature
2000V
200V
300C
65C to +150C
Operating Ratings
(Notes 1, 2)
Temperature Range
AV
DD
, DV
DD
AV
DD
DV
DD
|AV
SS
-DV
SS
|
V
RT
V
RB
V
IN
Voltage Range
20C
≤
T
A
≤
+75C
+4.75V to +5.25V
<
0.5V
0V to 100 mV
1.0V to V
DD
0V to 4.0V
V
RB
to V
RT
Converter Electrical Characteristics
The following specifications apply for AV
= DV
= +5.0V
, OE = 0V, V
RT
= +2.6V, V
= 0.6V, C
= 20 pF,
f
CLK
= 20MHz at 50% duty cycle.
Boldface limits apply for T
A
= T
MIN
to T
MAX
;
all other limits T
A
= 25C (Notes 7, 8)
Symbol
Parameter
Conditions
Typical
(Note 9)
Limits
(Note 9)
Units
DC Accuracy
INL
INL
DNL
DNL
Integral Non Linearity
Integral Non Linearity
Differential Non Linearity
Differential Non Linearity
Missing Codes
Top Offset
Bottom Offset
Video Accuracy
f
CLK
= 20 MHz
f
CLK
= 30 MHz
f
CLK
= 20 MHz
f
CLK
= 30 MHz
±
0.5
±
1.0
±
0.35
±
1.0
±
1.3
LSB( max)
LSB( max)
LSB( max)
LSB( max)
(max)
mV
mV
±
0.75
0
E
OT
E
OB
24
+37
DP
Differential Phase Error
f
in
= 4.43 MHz sine wave,
f
CLK
= 17.7 MHz
f
in
= 4.43 MHz sine wave,
f
CLK
= 17.7 MHz
0.5
Degree
DG
Differential Gain Error
0.4
%
Analog Input and Reference Characteristics
V
IN
Input Range
2.0
V
RB
V
RT
V(min)
V(max)
C
IN
V
IN
Input Capacitance
V
IN
= 1.5V + 0.7Vrms
(CLK
LOW)
(CLK
HIGH)
4
pF
11
R
IN
BW
R
RT
R
IN
Input Resistance
Analog Input Bandwidth
Top Reference Resistor
>
1
120
360
300
M
MHz
(min)
(max)
mA (min)
mA(max)
mA (min)
mA(max)
R
REF
Reference Ladder
Resistance
V
RT
to V
RB
200
400
R
RB
Bottom Reference Resistor
90
I
REF
Reference Ladder Current
V
RT
=V
RTS
, V
RB
=V
RBS
7
4.8
9.3
5.4
10.5
V
RT
=V
RTS
,V
RB
=AV
SS
8
V
RT
Reference Top Self Bias
Voltage
V
RT
connected to V
RTS
V
RB
connected to V
RBS
2.6
V
A
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