參數(shù)資料
型號(hào): ADC1175-50
廠商: National Semiconductor Corporation
英文描述: 8-Bit, 50 MSPS, 125 mW A/D Converter
中文描述: 8位,50 MSPS的,125毫瓦的A / D轉(zhuǎn)換器
文件頁(yè)數(shù): 3/17頁(yè)
文件大?。?/td> 487K
代理商: ADC1175-50
Pin Descriptions and Equivalent Circuits
(Continued)
Pin
No.
Symbol
Equivalent Circuit
Description
22
V
RBS
Reference Bottom Bias with internal pull down
resistor. Short to V
RB
to self bias the reference
ladder.
1
OE
CMOS/TTL compatible Digital input that, when low,
enables the digital outputs of the ADC1175. When
high, the outputs are in a high impedance state.
12
CLK
CMOS/TTL compatible digital clock Input. V
IN
is
sampled on the falling edge of CLK input.
3 thru
10
D0-D7
Conversion data digital Output pins. D0 is the LSB,
D7 is the MSB. Valid data is output just after the
rising edge of the CLK input. These pins are
enabled by bringing the OE pin low.
11, 13
DV
DD
Positive digital supply pin. Connect to a clean, quiet
voltage source of +5V. AV
DD
and DV
DD
should have
a common source and be separately bypassed with
a 10μF capacitor and a 0.1μF ceramic chip
capacitor. See Section 3.0 for more information.
The ground return for the digital supply. AV
SS
and
DV
SS
should be connected together close to the
ADC1175.
Positive analog supply pin. Connected to a clean,
quiet voltage source of +5V. AV
DD
and DV
DD
should
have a common source and be separately bypassed
with a 10 μF capacitor and a 0.1 μF ceramic chip
capacitor. See Section 3.0 for more information.
The ground return for the analog supply. AV
SS
and
DV
SS
should be connected together close to the
ADC1175 package.
2, 24
DV
SS
14,
15, 18
AV
DD
20, 21
AV
SS
A
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