- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄223307 > ADC1113S125HN (NXP Semiconductors N.V.) Single 11 bits ADC; 125Msps; serial JESD204A PDF資料下載
參數(shù)資料
| 型號： | ADC1113S125HN |
| 廠商： | NXP Semiconductors N.V. |
| 元件分類： | 外設(shè)及接口 |
| 英文描述： | Single 11 bits ADC; 125Msps; serial JESD204A |
| 封裝： | ADC1113S125HN/C1<SOT1152-1 (HVQFN32R)|<<http://www.nxp.com/packages/SOT1152-1.html<1<Always Pb-free,;ADC1113S125HN/C1<SOT1152-1 (HVQFN32R)|<<http://www.nxp.com/packages/S |
| 文件頁數(shù)： | 4/38頁 |
| 文件大?。?/td> | 648K |
| 代理商： | ADC1113S125HN |
第1頁第2頁第3頁當前第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁
ADC1113S125
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 1 — 15 March 2011
12 of 38
NXP Semiconductors
ADC1113S125
Single 11-bit ADC; serial JESD204A interface
11. Application information
11.1 Analog inputs
11.1.1 Input stage description
The analog input of the ADC1113S supports a differential or a single-ended input drive.
Optimal performance is achieved using differential inputs with the common-mode input
voltage (VI(cm)) on pins INP and INM set to 0.5VDDA.
The full-scale analog input voltage range is configurable between 1 V (p-p) and 2 V (p-p)
via a programmable internal reference (see Section 11.2 and Table 21).
Figure 6 shows the equivalent circuit of the sample-and-hold input stage, including
ElectroStatic Discharge (ESD) protection and circuit and package parasitics.
The sample phase occurs when the internal clock (derived from the clock signal on pin
CLKP/CLKM) is HIGH. The voltage is then held on the sampling capacitors. When the
clock signal goes LOW, the stage enters the hold phase and the voltage information is
transmitted to the ADC core.
11.1.2 Anti-kickback circuitry
Anti-kickback circuitry (RC filter in Figure 7) is needed to counteract the effects of a
charge injection generated by the sampling capacitance.
The RC filter is also used to filter noise from the signal before it reaches the sampling
stage. The value of the capacitor should be chosen to maximize noise attenuation without
degrading the settling time excessively.
Fig 6.
Input sampling circuit
005aaa185
INP
package
ESD
parasitics
switch
Ron = 15 Ω
Cs
switch
Ron = 15 Ω
INM
8
7
internal
clock
internal
clock
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ADC1213D065HN | Dual 12-bit ADC; 65 Msps |
| ADD223AB7 | FIBER OPTIC ADD/DROP MUX/DEMUX, LC/UPC CONNECTOR |
| ADE-ED7795/1+ | 100 MHz - 1536 MHz RF/MICROWAVE DOUBLE BALANCED MIXER |
| ADE-ED7861/1+ | 1 MHz - 1106 MHz RF/MICROWAVE DOUBLE BALANCED MIXER |
| ADE07 | SLIDE DIP SWITCH-7SWITCHES, SPST, LATCHED,THROUGH HOLE-STRAIGHT |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADC1113S125HN/C1,5 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC SGL 11BT ADC 125MSPS SERIAL JESD204A RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADC1113S125HN/C1,551 | 制造商:NXP Semiconductors 功能描述:Bulk 制造商:NXP Semiconductors 功能描述:0 |
| ADC1113S125HN-C1 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADC1113S125HN-C18 | 制造商:Integrated Device Technology Inc 功能描述:HVQFN32 - Tape and Reel |
發(fā)布緊急采購，3分鐘左右您將得到回復。