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參數(shù)資料
| 型號： | ADC10732CIWM |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | ADC |
| 英文描述： | 10-Bit Plus Sign Serial I/O A/D Converters with Mux, |
| 中文描述： | 2-CH 10-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO20 |
| 封裝： | SOP-20 |
| 文件頁數(shù)： | 3/27頁 |
| 文件大小： | 556K |
| 代理商： | ADC10732CIWM |
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Ordering Information
Industrial Temperature Range
40C
≤
T
A
≤
+85C
ADC10731CIWM
ADC10732CIWM
ADC10734CIMSA
ADC10734CIWM
ADC10738CIWM
Package
M16B
M20B
MSA20
M20B
M24B
Pin Descriptions
CLK
The clock applied to this input controls the suc-
cessive approximation conversion time interval,
the acquisition time and the rate at which the se-
rial data exchange occurs. The rising edge loads
the information on the DI pin into the multiplexer
address shift register. This address controls
which channel of the analog input multiplexer
(MUX) is selected. The falling edge shifts the
data resulting from the A/D conversion out on
DO. CS enables or disables the above functions.
The clock frequency applied to this input can be
between 5 kHz and 3 MHz.
DI
This is the serial data input pin. The data applied
to this pln is shifted by CLK into the multiplexer
address register. Tables 1, 2, 3 show the multi-
plexer address assignment.
DO
The data output pin. The A/D conversion result
(DB0-SIGN) are clocked out by the failing edge
of CLK on this pin.
CS
This is the chip select input pin. When a logic low
is applied to this pin, the rising edge of CLK
shifts the data on DI into the address register.
This low also brings DO out of TRI-STATE after
a conversion has been completed.
PD
This is the power down input pin. When a logic
high is applied to this pin the A/D is powered
down. When a low is applied the A/D is powered
up.
SARS
This is the successive approximation register
status output pin. When CS is high this pin is in
TRI-STATE. With CS low this pin is active high
when a conversion is in progress and active low
at all other times.
CH0–CH7 These are the analog inputs of the MUX.Achan-
nel input is selected by the address information
at the DI pin, which is loaded on the rising edge
of CLK into the address register (see Tables 1, 2,
3).
The voltage applied to these inputs should not
exceed AV
or go below GND by more than
50 mV. Exceeding this range on an unselected
channel will corrupt the reading of a selected
channel.
COM
This pin is another analog input pln. It can be
used as a “pseudo ground” when the analog
multiplexer is single-ended.
V
REF
+
This is the positive analog voltage reference in-
put. In order to malntaln accuracy, the voltage
range V
REF
(V
REF
= V
REF
+–V
REF
) is 0.5 V
to
5.0 V
REF
+ cannot exceed
AV
+
+50 mV.
V
REF
The negative voltage reference input. In order to
maintain accuracy, the voltage at this pin must
not go below GND 50 mV or exceed AV
+
+ 50 mV.
These are the analog and digital power supply
pins. These pins should be tied to the same
power supply and bypassed separately. The op-
erating voltage range of AV
+
and DV
+
is 4.5 V
DC
to 5.5 V
DC
.
This is the digital ground pin.
This is the analog ground pin.
AV
+
, DV
+
DGND
AGND
www.national.com
3
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADC10732CIWM/NOPB | 制造商:Texas Instruments 功能描述:ADC Single SAR 74ksps 10-bit+Sign Serial 20-Pin SOIC W |
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| ADC10732CIWMX/NOPB | 制造商:Texas Instruments 功能描述:ADC Single SAR 74ksps 10-bit+Sign Serial 20-Pin SOIC W T/R |
| ADC10734 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:10-Bit Plus Sign Serial I/O A/D Converters with Mux, Sample/Hold and Reference |
| ADC10734CIMSA | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:10-Bit Plus Sign Serial I/O A/D Converters with Mux, |
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