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參數(shù)資料
| 型號： | ADC1061CIWM |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | ADC |
| 英文描述： | 10-Bit High-Speed レP-Compatible A/D Converter with Track/Hold Function |
| 中文描述： | 1-CH 10-BIT FLASH METHOD ADC, PARALLEL ACCESS, PDSO20 |
| 封裝： | SOP-20 |
| 文件頁數(shù)： | 7/11頁 |
| 文件大小： | 320K |
| 代理商： | ADC1061CIWM |
Functional Description
(Continued)
The remaining four LSBs may now be determined using the
same sixteen comparators that were used for the first flash
conversion. The MSB Ladder tap voltage just below the input
voltage (as determined by the first flash) is subtracted from
the input voltage and compared with the tap points on the
sixteen LSB Ladder resistors. The result of this second flash
conversion is then decoded, and the full 10-bit result is
latched.
Note that the sixteen comparators used in the first flash con-
version are reused for the second flash. Thus, the half-flash
conversion techniques used in the ADC1061 needs only a
small fraction of the number of comparators that would be re-
quired for a traditional flash converter, and far fewer than
would be used in a conventional half-flash approach. This al-
lows the ADC1061 to perform high-speed conversions with-
out excessive power drain.
Applications Information
1.0 Modes of Operation
The ADC1061 has two basic digital interface modes. These
are illustrated in Figure 1 and Figure 2
MODE 1
In this mode, the S /H pin controls the start of conversion.
S /H is pulled low for a minimum of 250 ns. This causes the
comparators in the “coarse” flash converter to become ac-
tive. When S /H goes high, the result of the coarse conver-
sion is latched and the “fine” conversion begins. After ap-
proximately 1.2 μs (1.8 μs maximum), INT goes low,
indicating that the conversion results are latched and can be
read by pulling RD low. Note that CS must be low to enable
S /H or RD . CS is internally “ANDed” with the sample and
read control signals; the input voltage is sampled when CS
and S /H are low, and is read when CS and RD are low.
MODE 2
In Mode 2, also called “RD mode”, the S /H and RD pins are
tied together. A conversion is initiated by pulling both pins
low. TheADC1061 samples the input voltage and causes the
coarse comparators to become active. An internal timer then
terminates the coarse conversion and begins the fine con-
version.
About 1.8 μs (2.4 μs maximum) after S /H and RD are pulled
low, INT goes low, indicating that the conversion is complete.
Approximately 20 ns later the data appearing on the
TRI-STATE output pins will be valid. Note that data will ap-
pear on these pins throughout the conversion, but will be
valid only after INT goes low.
DS010559-13
FIGURE 3. Block Diagram of the Modified Half-Flash Converter Architecture
www.national.com
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