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參數(shù)資料
| 型號： | ADC1038 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | 10-Bit Serial I/O A/D Converter with Analog Multiplexer |
| 中文描述： | 10位串行I /辦公自動(dòng)化/ D的模擬多路復(fù)用器 |
| 文件頁數(shù)： | 3/13頁 |
| 文件大小： | 551K |
| 代理商： | ADC1038 |
Electrical Characteristics
(Continued)
The following specifications apply for V
CC
= +5.0V, V
= +4.6V, f
S
= 700 kHz, and f
C
= 3 MHz unless otherwise specified.
Boldface limits apply for T
A
= T
J
= T
MIN
to T
MAX
; all other limits T
A
= T
J
= 25C.
Symbol
Parameter
Conditions
Typical
(Note 8)
Limit
(Note 9)
Units
(Limits)
AC CHARACTERISTICS
f
C
Conversion Clock (C
CLK
)
Frequency
f
S
Serial Data Clock (S
CLK
)
Frequency (Note 13)
0.7
4.0
183
622
2
MHz (min)
MHz (max)
kHz (min)
kHz (min)
MHz (max)
(max)
3.0
f
C
= 3 MHz, R/L = “0”
f
C
= 3 MHz, R/L = “1”
f
C
= 3 MHz, R/L = “0” or R/L = “1”
Not Including MUX Addressing and
Analog Input Sampling Times
After Address is Latched,CS = Low
1.0
T
C
Conversion Time
41 (1/f
C
)
+ 200 ns
4.5 (1/f
S
)
+ 200 ns
200
t
CA
Analog Sampling Time
(max)
t
ACC
Access Time Delay from CS or OE
Falling Edge to DO Data Valid
Set-up Time of CS Falling
Edge to S
CLK
Rising Edge
Delay from OE or CS Rising
Edge to DO TRI-STATE
DI Hold Time from S
CLK
Rising Edge
DI Set-up Time to S
CLK
Rising Edge
DO Hold Time from S
CLK
Falling Edge
Delay from S
CLK
Falling
Edge to DO Data Valid
DO Rise Time
OE = “0”
100
ns (max)
t
SET-UP
75
150
ns (min)
t
1H
, t
0H
R
L
= 3 k
, C
L
= 100 pF
100
120
ns (max)
t
HDI
t
SDI
t
HDO
t
DDO
0
50
100
10
250
ns (min)
ns (min)
ns (min)
ns (max)
50
70
150
R
L
= 30 k
, C
L
= 100 pF
R
L
= 30 k
, C
L
= 100 pF
t
RDO
R
L
= 30 k
,
C
L
= 100 pF
R
L
= 30 k
,
C
L
= 100 pF
Analog Inputs (CH0–CH7)
All Other Inputs
TRI-STATE to High
Low to High
TRI-STATE to Low
High to Low
35
75
35
75
50
7.5
75
150
75
150
ns (max)
ns (max)
ns (max)
ns (max)
pF
pF
t
FDO
DO Fall Time
C
IN
Input Capacitance
Note 1:
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur.
Note 2:
Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. For guaranteed specifications and
test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may de-
grade when the device is not operated under the listed test conditions.
Note 3:
All voltages are measured with respect to AGND and DGND, unless otherwise specified.
Note 4:
When the input voltage (V
) at any pin exceeds the power supplies (V
<
DGND, or V
>
V
) the current at that pin should be limited to 5 mA. The 20 mA
maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 5 mA to four pins.
Note 5:
The maximum power dissipation must be derated at elevated temperatures and is dictated by T
Jmax
,
θ
JA
and the ambient temperature, T
A
. The maximum
allowable power dissipation at any temperature is P
= (T
T
)/
θ
or the number given in the Absolute Maximum Ratings, whichever is lower. For this device,
T
Jmax
= 125C. The typical thermal resistance (
θ
JA
) when board mounted is 64C/W.
Note 6:
Human body model, 100 pF capacitor discharged through a 1.5 k
resistor.
Note 7:
See AN450 “Surface Mounting Methods and Their Effect on Product Reliability” or Linear Databook section “Surface Mount” for other methods of soldering
surface mount devices.
Note 8:
Typicals are at T
J
= 25C and represent most likely parametric norm.
Note 9:
Limits are guaranteed to National’s AOQL (Average Outgoing Quality Level).
Note 10:
Total unadjusted error includes offset, full-scale, linearity, multiplexer, and hold step errors.
Note 11:
Two on-chip diodes are tied to each analog input. They will forward-conduct for analog input voltages one diode drop below ground or one diode drop
greater than V
supply. Be careful during testing at low V
levels (4.5V), as high level analog inputs (5V) can cause an input diode to conduct, especially at el-
evated temperatures, which will cause errors for analog inputs near full-scale. The spec allows 50 mV forward bias of either diode; this means that as long as the
analog V
does not exceed the supply voltage by more than 50 mV, the output code will be correct. Exceeding this range on an unselected channel will corrupt the
reading of a selected channel. To achieve an absolute 0 V
DC
to 5 V
DC
input voltage range will therefore require a minimum supply voltage of 4.950 V
DC
over tem-
perature variations, initial tolerance and loading.
Note 12:
Channel leakage current is measured after the channel selection.
Note 13:
In order to synchronize the serial data exchange properly, SARS needs to go low after completion of the serial I/O data exchange. If this does not occur
the output shift register will be reset and the correct output data lost. The minimum limit for S
CLK
will depend on C
CLK
frequency and whether right-justified or
left-justified, and can be determined by the following equations:
f
S
>
(8.5/41) (f
C
) with right-justification (R/L = “1”) and f
S
>
(2.5/41) (f
C
) with left-justification (R/L = “0”).
www.national.com
3
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