參數(shù)資料
型號: ADC10221CIVT
廠商: NATIONAL SEMICONDUCTOR CORP
元件分類: ADC
英文描述: 10-Bit, 15 MSPS, 98 mW A/D Converter with Internal Sample and Hold
中文描述: 1-CH 10-BIT RESISTANCE LADDER ADC, PARALLEL ACCESS, PQFP32
封裝: TQFP-32
文件頁數(shù): 10/16頁
文件大小: 414K
代理商: ADC10221CIVT
Timing Diagram
Functional Description
The ADC10221 maintains excellent dynamic performance
for input signals up to half the clock frequency. The use of an
internal sample-and-hold amplifier (SHA) enables sustained
dynamic performance for signals of input frequency beyond
the clock rate, lowers the converter’s input capacitance and
reduces the number of external components required.
The analog signal at V
that is within the voltage range set
by V
+ S and V
S are digitized to ten bits at up to
25 MSPS. Input voltages below V
S will cause the out-
put word to consist of all zeroes. Input voltages above V
REF
+
S will cause the output word to consist of all ones. V
REF
+ S
has a range of 2.3 to 4.0 Volts, while V
S has a range of
1.3 to 3.0 Volts. V
+ S should always be at least 1.0 Volt
more positive than V
REF
S.
Data is acquired at the falling edge of the clock and the digi-
tal equivalent of that data is available at the digital outputs
2.0 clock cycles plus t
later. TheADC10221 will convert as
long as the clock signal is present at pin 9 and the PD pin is
low. The Output Enable pin (OE), when low, enables the out-
put pins. The digital outputs are in the high impedance state
when the OE pin is low or the PD pin is high.
DS101038-15
FIGURE 1. ADC10221 Timing Diagram
DS101038-17
FIGURE 2. AC Test Circuit
DS101038-16
FIGURE 3. t
EN
, t
DIS
Test Circuit
A
www.national.com
10
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