參數(shù)資料
型號(hào): ADC10221
廠商: National Semiconductor Corporation
英文描述: 10-Bit, 15 MSPS, 98 mW A/D Converter with Internal Sample and Hold
中文描述: 10位,15 MSPS的98毫瓦的A / D內(nèi)部采樣與保持器
文件頁(yè)數(shù): 3/16頁(yè)
文件大?。?/td> 414K
代理商: ADC10221
Pin Descriptions and Equivalent Circuits
Pin
No.
Analog I/O
Symbol
Equivalent Circuit
Description
30
V
IN
Analog Input signal to be converted. Conversion
range is V
REF
+
S to V
REF
S.
31
V
REF
+
F
Analog input that goes to the high side of the
reference ladder of the ADC. This voltage should
force V
REF
+
S to be in the range of 2.3V to 4.0V.
Analog output used to sense the voltage at the top
of the ADC reference ladder.
Analog input that goes to the low side of the
reference ladder of the ADC. This voltage should
force V
REF
S to be in the range of 1.3V to 3.0V.
Analog output used to sense the voltage at the
bottom of the ADC reference ladder.
32
V
REF
+
S
2
V
REF
F
1
V
REF
S
9
CLK
Converter digital clock input. V
IN
is sampled on the
falling edge of CLK input.
8
PD
Power Down input. When this pin is high, the
converter is in the Power Down mode and the data
output pins are in a high impedance state.
26
OE
Output Enable pin. When this pin and the PD pin
are low, the output data pins are active. When this
pin or the PD pin is high, the output data pins are in
a high impedance state.
14
thru
19
and
22
thru
25
D0 -D9
Digital Output pins providing the 10 bit conversion
results. D0 is the LSB, D9 is the MSB. Valid data is
present just after the falling edge of the CLK input.
3, 7,
28
V
A
Positive analog supply pins. These pins should be
connected to a clean, quiet voltage source of +5V.
V
A
and V
D
should have a common supply and be
separately bypassed with 10μF to 50μF capacitors
in parallel with 0.1μF capacitors.
Positive digital supply pins. These pins should be
connected to a clean, quiet voltage source of +5V.
V
A
and V
D
should have a common supply and be
separately bypassed with 10μF to 50μF capacitors
in parallel with 0.1μF capacitors.
5, 10
V
D
A
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