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參數(shù)資料
| 型號： | ADC1005S060TS |
| 廠商： | NXP Semiconductors N.V. |
| 元件分類： | 外設(shè)及接口 |
| 英文描述： | Single 10 bits ADC, up to 60 MHz |
| 封裝： | ADC1005S060TS/C1<SOT341-1 (SSOP28)|<<http://www.nxp.com/packages/SOT341-1.html<1<Always Pb-free,;ADC1005S060TS/C1<SOT341-1 (SSOP28)|<<http://www.nxp.com/packages/SOT341-1 |
| 文件頁數(shù)： | 9/19頁 |
| 文件大小： | 105K |
| 代理商： | ADC1005S060TS |
ADC1005S060_2
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 02 — 13 August 2008
9 of 19
NXP Semiconductors
ADC1005S060
Single 10 bits ADC, up to 60 MHz
[1]
The rise and fall times of the clock signal must not be less than 0.5 ns.
[2]
The input admittance is
[3]
Analog input voltages producing code 0 up to and including code 1023:
a) V
offset
BOTTOM is the difference between the analog input which produces data equal to 00 and the reference voltage on pin RB
(V
RB
) at T
amb
= 25
°
C.
b) V
offset
TOP is the difference between the reference voltage on pin RT (V
RT
) and the analog input which produces data outputs equal
to code 1023 at T
amb
= 25
°
C
.
To ensure the optimum linearity performance of such a converter architecture the lower and upper extremities of the converter reference
resistor ladder are connected to pins RB and RT via offset resistors R
OB
and R
OT
as shown in
Figure 3
.
V
V
–
OB
L
OT
[4]
a) The current flowing into the resistor ladder is
and the full-scale input range at the converter, to cover code 0
to 1023 is
b) Since R
L
, R
OB
and R
OT
have similar behavior with respect to process and temperature variation, the ratio
will be kept reasonably constant from device to device. Consequently, variation of the output codes at a given input voltage depends
mainly on the difference V
RT
V
RB
and its variation with temperature and supply voltage. When several ADCs are connected in
parallel and fed with the same reference source, the matching between each of them is optimized.
[5]
[6]
The analog bandwidth is defined as the maximum input sine wave frequency which can be applied to the device. No glitches greater
than 2 LSB, neither any significant attenuation are observed in the reconstructed signal.
[7]
The analog input settling time is the minimum time required for the input signal to be stabilized after a sharp full-scale input (square
wave signal) in order to sample the signal and obtain correct output data.
[8]
Effective bits are obtained via a Fast Fourier Transform (FFT) treatment taking 8000 acquisition points per equivalent fundamental
period. The calculation takes into account all harmonics and noise up to half the clock frequency (Nyquist frequency). Conversion to
signal-to-noise ratio: S/N = ENOB
×
6.02 + 1.76 dB.
[9]
Intermodulation measured relative to either tone with analog input frequencies of 4.3 MHz and 4.5 MHz. The two input signals have the
same amplitude and the total amplitude of both signals provides full-scale to the converter.
[10] Output data acquisition: the output data is available after the maximum delay time of t
d(o)
. NXP recommends the lowest possible output
load. These parameters are guaranteed by characterization and not by production test.
C
L
SR
3-state output delay times (f
clk
= 60 MHz; V
CCO
= 3.3 V); see
Figure 5
t
dZH
float to active
HIGH delay time
t
dZL
float to active
LOW delay time
t
dHZ
active HIGH to
float delay time
t
dLZ
active LOW to
float delay time
load capacitance
slew rate
-
0.2
-
0.3
10
-
pF
V/ns
V
CCO
= 2.7 V
-
16
20
ns
-
30
34
ns
-
25
30
ns
-
23
27
ns
Table 6.
V
CCA
= 4.75 V to 5.25 V; V
CCD
= 4.75 V to 5.25 V; AGND and DGND shorted together; T
amb
= 0
°
C to 70
°
C; typical values
measured at V
CCA
= V
CCD
= 5 V; V
CCO
= 3.3 V; V
RB
= 1.3 V; V
RT
= 3.7 V; C
L
= 10 pF and T
amb
= 25
°
C unless otherwise
specified.
Symbol
Parameter
Conditions
Characteristics
…continued
Min
Typ
Max
Unit
Y
i
1
R
i
----
j
ω
C
i
+
+
I
----------------------------------------
=
V
I
R
L
I
L
×
R
L
OB
OT
----------------------------------------
V
RT
V
RB
+
(
)
×
0.8375
V
RT
V
RB
–
(
)
×
=
=
=
R
L
OB
OT
----------------------------------------
E
G
V
--------------------------------------------------------
V
–
i p
(
)
V
p
–
)
–
p
–
(
)
100
×
=
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|---|---|
| ADC1005S060TS/C1,1 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC ADC Single 60MSPS 10bit Parallel 28pin RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADC1005S060TS/C1,118 | 制造商:NXP Semiconductors 功能描述:Cut Tape 制造商:NXP Semiconductors 功能描述:0 |
| ADC1005S060TS/C1’1 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC ADC Single 60MSPS 10Bit Parallel 28Pin RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADC1005S060TS/C1'1 | 功能描述:10 Bit Analog to Digital Converter 1 Input 28-SSOP 制造商:nxp semiconductors 系列:- 包裝:管件 零件狀態(tài):有效 位數(shù):10 采樣率（每秒）:60M 輸入數(shù):1 輸入類型:單端 數(shù)據(jù)接口:并聯(lián) 配置:ADC 無線電 - S/H:ADC:- A/D 轉(zhuǎn)換器數(shù):1 架構(gòu):- 參考類型:外部 電壓 - 電源，模擬:5V 電壓 - 電源，數(shù)字:2.7 V ~ 3.6 V 特性:- 工作溫度:-40°C ~ 85°C 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應(yīng)商器件封裝:28-SSOP 標(biāo)準(zhǔn)包裝:47 |
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