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參數(shù)資料
| 型號(hào)： | ADC1001CCJ |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | ADC |
| 英文描述： | 10-Bit P Compatible A/D Converter |
| 中文描述： | 1-CH 10-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, CDIP20 |
| 封裝： | 0.300 INCH, SIDE BRAZED, DIP-20 |
| 文件頁(yè)數(shù)： | 3/9頁(yè) |
| 文件大?。?/td> | 201K |
| 代理商： | ADC1001CCJ |
DC Electrical Characteristics
The following specifications apply for V
CC
=5 V
DC
and T
MIN
≤
T
A
≤
T
MAX
, unless otherwise specified.
Symbol
Parameter
CONTROL INPUTS
[Note: CLK IN is the input of a Schmitt trigger circuit and is therefore specified separately]
V
IN
(1)
Logical “1” Input Voltage
V
CC
=5.25 V
DC
(Except CLK IN)
V
IN
(0)
Logical “0” Input Voltage
V
CC
=4.75 V
DC
(Except CLK IN)
I
IN
(1)
Logical “1” Input Current
V
IN
=5 V
DC
(All Inputs)
I
IN
(0)
Logical “0” input Current
V
IN
=0 V
DC
(All Inputs)
CLOCK IN
V
T
+
CLK IN Positive Going
Threshold Voltage
V
T
CLK IN Negative Going
Threshold Voltage
V
H
CLK IN Hysteresis
(V
T
+)(V
T
)
OUTPUTS AND INTR
V
OUT
(0)
Logical “0” Output Voltage
I
OUT
=1.6 mA, V
CC
=4.75 V
DC
V
OUT
(1)
Logical “1” Output Voltage
I
O
=360 μA, V
CC
=4.75 V
DC
I
O
=10 μA, V
CC
=4.75 V
DC
I
OUT
TRI-STATE Disabled Output
V
OUT
=0.4 V
DC
Leakage (All Data Buffers)
V
OUT
=5 V
DC
I
SOURCE
V
OUT
Short to GND, T
A
=25C
I
SINK
V
OUT
Short to V
CC
, T
A
=25C
POWER SUPPLY
I
CC
Supply Current (Includes
f
CLK
=410 kHz,
Ladder Current)
V
REF
/2=NC, T
A
=25C
and CS =1
Conditions
MIn
Typ
Max
Units
2.0
15
V
DC
0.8
V
DC
0.005
1
μA
DC
1
0.005
μA
DC
2.7
3.1
3.5
V
DC
1.5
1.8
2.1
V
DC
0.6
1.3
2.0
V
DC
0.4
V
DC
V
DC
V
DC
μA
DC
μA
DC
mA
DC
mA
DC
2.4
4.5
0.1
0.1
6
16
100
3
4.5
9.0
2.5
5.0
mA
Note 1:
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating
the device beyond its specified operating conditions.
Note 2:
All voltages are measured with respect to GND, unless otherwise specified. The separate A GND point should always be wired to the D GND.
Note 3:
A zener diode exists, internally, from V
CC
to GND and has a typical breakdown voltage of 7 V
DC
.
Note 4:
For V
()
≥
V
(+) the digital output code will be all zeros. Two on-chip diodes are tied to each analog input (see Block Diagram) which will forward conduct
for analog input voltages one diode drop below ground or one diode drop greater than the V
supply. Be careful, during testing at low V
levels (4.5V), as high
level analog inputs (5V) can cause this input diode to conduct — especially at elevated temperatures, and cause errors for analog inputs near fullscale. The spec al-
lows 50 mV forward bias of either diode. This means that as long as the analog V
does not exceed the supply voltage by more than 50 mV, the output code will
be correct. To achieve an absolute 0 V
DC
to 5 V
DC
input voltage range will therefore require a minimum supply voltage of 4.950 V
DC
over temperature variations, initial
tolerance and loading.
Note 5:
With an asynchronous start pulse, up to 8 clock periods may be required before the internal clock phases are proper to start the conversion process. The
start request is internally latched, see Figure 3 .
Note 6:
The CS input is assumed to bracket the WR strobe input and therefore timing is dependent on the WR pulse width. An arbitrarily wide pulse width will hold
the converter in a reset mode and the start of conversion is initiated by the low to high transition of the WR pulse (see Timing Diagrams).
Note 7:
All typical values are for T
A
=25C.
Note 8:
Accuracy is guaranteed at f
CLK
=410 kHz. At higher clock frequencies accuracy can degrade.
Note 9:
The V
pin is the center point of a two resistor divider (each resistor is 2.4k
) connected from V
CC
to ground. Total ladder input resistance is the sum
of these two equal resistors.
Note 10:
Human body model, 100 pF discharged through a 1.5 k
resistor.
www.national.com
3
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