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參數(shù)資料
| 型號： | ADC1001CCJ-1 |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | ADC |
| 英文描述： | RES 27K 1/4W 5% CF |
| 中文描述： | 1-CH 10-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, CDIP20 |
| 封裝： | 0.300 INCH, SIDE BRAZED, DIP-20 |
| 文件頁數(shù)： | 2/9頁 |
| 文件大?。?/td> | 201K |
| 代理商： | ADC1001CCJ-1 |
Absolute Maximum Ratings
(Notes 1, 2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (V
CC
) (Note 3)
Logic Control Inputs
Voltage at Other Inputs and Outputs
Storage Temperature Range
Package Dissipation at T
A
=25C
6.5V
0.3V to +18V
0.3V to (V
CC
+0.3V)
65C to +150C
875 mW
Lead Temp. (Soldering, 10 seconds)
ESD Susceptibility (Note 10)
300C
800V
Operating Conditions
(Notes 1, 2)
Temperature Range
ADC1001CCJ
ADC1001CCJ-1
Range of V
CC
T
MIN
≤
T
A
≤
T
MAX
40C
≤
T
A
≤
+85C
0C
≤
T
A
≤
+70C
4.5 V
DC
to 6.3 V
DC
Converter Characteristics
Converter Specifications:
V
CC
=5 V
DC
, V
REF
/2=2.500 V
DC
, T
MIN
≤
T
A
≤
T
MAX
and f
CLK
=410 kHz unless otherwise specified.
Parameter
Conditions
Linearity Error
Zero Error
Full-Scale Error
Total Ladder Resistance (Note 9)
Input Resistance at Pin 9
Analog Input Voltage Range
(Note 4) V(+) or V()
DC Common-Mode Error
Over Analog Input Voltage Range
Power Supply Sensitivity
V
CC
=5 V
DC
±
5% Over
Allowed V
IN
(+) and V
IN
()
Voltage Range (Note 4)
MIn
Typ
Max
±
1
±
2
±
2
Units
LSB
LSB
LSB
K
V
DC
LSB
LSB
2.2
4.8
GND0.05
V
CC
+0.05
±
1
8
±
1
8
AC Electrical Characteristics
Timing Specifications:
V
CC
=5 V
DC
and T
A
=25C unless otherwise specified.
Symbol
Parameter
T
c
Conversion Time
Conditions
MIn
80
195
100
40
Typ
Max
90
220
1260
60
4600
Units
1/f
CLK
μs
kHz
%
conv/s
(Note 5)
f
CLK
=410 kHz
(Note 8)
f
CLK
Clock Frequency
Clock Duty Cycle
Conversion Rate In Free-Running
Mode
Width of WR Input (Start Pulse
Width)
Access Time (Delay from
Falling Edge of RD to Output
Data Valid)
TRI-STATE
Control (Delay
from Rising Edge of RD to
Hi-Z State)
Delay from Falling Edge
of WR or RD to Reset of INTR
INTR to 1st Read Set-Up Time
Input Capacitance of Logic
Control Inputs
TRI-STATE Output
Capacitance (Data Buffers)
CR
INTR tied to WR with
CS =0 V
DC
, f
CLK
=410 kHz
CS =0 V
DC
(Note 6)
t
W(WR)L
150
ns
t
ACC
C
L
=100 pF
170
300
ns
t
1H
, t
0H
C
L
=10 pF, R
L
=10k
(See TRI-STATE Test
Circuits)
125
200
ns
t
WI
, t
RI
300
450
ns
t
1rs
C
IN
550
400
5
ns
pF
7.5
C
OUT
5
7.5
pF
www.national.com
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