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參數(shù)資料
| 型號(hào)： | ADC09R03 |
| 元件分類： | ADC |
| 英文描述： | Analog to Digital Converter |
| 中文描述： | 模數(shù)轉(zhuǎn)換器 |
| 文件頁(yè)數(shù)： | 1/4頁(yè) |
| 文件大小： | 35K |
| 代理商： | ADC09R03 |
1
DAC/ADC
AMI 0.6 micron CMOS
ADC09R03
5V, 9 Bit 60 KSPS, Resistive Ladder ADC
Features
Maximum range of the input is 0.5 to 3.5 volts above
analog ground
Max clock input 600 kHz
Low-Power Mode
Sleep Mode
The converter is operated by one single power supply
Functional Block Diagram
Notes: VIN: Input Voltage
VREF: Reference Voltage
CLK: Clock Input
CMPPWRDN: Low-Power Mode
PWRDN: Sleep Mode
RESET
Q0-Q8: Digital Outputs (Q8 is MSB, Q0 is LSB)
VALID: Indicates the finish of the current conversion
V5: Analog supply voltage
VL: Logic supply voltage
AGND: Analog Ground
DGND: Digital Ground
General Description
The ADC09R03 is realized as a resistive ladder
architecture. The part operates on one single 5V supply.
The 9-Bit ADC is designed to run in a continuous mode.
No control signals are required to begin conversions.
Each conversion requires 10 clock-cycles, for a maximum
conversion rate of 60 kHz. The VALID signal goes high at
the completion of the conversion, and the data is latched
at the outputs until the next assertion of VALID.
In order to decrease power consumption, the ADC09R03
can be put into one of two low-power modes, sleep or
low-power. This ultra-low power characteristic makes the
ADC09R03 ideal for portable applications.
Applications
Low power portable applications
Instrumentation
DSP control loops
Audio processing
Low speed data acquisition
Product Highlights
Ultra-low power operation.
Hybrid design of both resistor network and capacitor
network guarantees highest accuracy.
External reference.
Low-power and sleep mode.
The ADC09R03 operates on a single 5V supply.
Part is realized in AMI's 0.6
1.5
μ
process allows operation at higher voltages.
μ
process. A version in AMI's
Valid
Out
Q0-Q8
VREF
Input
Clk
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