參數(shù)資料
型號(hào): ADC08832IWM
廠商: NATIONAL SEMICONDUCTOR CORP
元件分類: ADC
英文描述: 8-Bit Serial I/O CMOS A/D Converters with Multiplexer and Sample/Hold Function
中文描述: 2-CH 8-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO14
封裝: SOIC-14
文件頁(yè)數(shù): 4/23頁(yè)
文件大?。?/td> 486K
代理商: ADC08832IWM
Electrical Characteristics
(Continued)
The following specifications apply for V
= V
= +5V
DC
, and f
CLK
= 2 MHz unless otherwise specified.
Boldface limits
apply for T
A
= T
J
= T
MIN
to T
MAX
;
all other limits T
A
= T
J
= 25C.
Symbol
Parameter
Conditions
Typical
(Note 8)
Limits
(Note 9)
Units
(Limits)
DC CHARACTERISTICS
I
CC
Supply Current
CLK = V
CC
ADC08831
CS = V
CC
CS = LOW
CS = V
CC
CS = LOW
0.6
1.7
1.3
2.4
1.0
2.4
1.8
3.5
mA (max)
mA (max)
mA (max)
mA (max)
I
CC
Supply Current
CLK = V
CC
(Note 16)
ADC08832
Electrical Characteristics
The following specifications apply for V
= V
= +5 V
DC
, and t
r
= t
f
= 20 ns unless otherwise specified.
Boldface limits
apply for T
A
= T
J
= T
MIN
to T
MAX
;
all other limits T
A
= T
J
= 25C.
Symbol
Parameter
Conditions
Typical
(Note 8)
Limits
(Note 9)
2
40
60
8
4
Units
(Limits)
MHz (max)
% (min)
% (max)
1/f
CLK
(max)
μs (max)
1/f
CLK
(max)
ns (min)
f
CLK
Clock Frequency
Clock Duty Cycle
(Note 14)
Conversion Time (Not Including MUX
Addressing Time)
Acquisition Time
CS Falling Edge or Data Input
Valid to CLK Rising Edge
Data Input Valid after CLK
Rising Edge
CLK Falling Edge to Output
Data Valid (Note 15)
T
C
f
CLK
= 2MHz
t
CA
t
SET-UP
1
2
25
t
HOLD
20
ns (min)
t
pd1
, t
pd0
C
L
= 100 pF:
Data MSB First
Data LSB First
C
L
= 10 pF, R
L
= 10 k
(see TRI-STATE Test Circuits)
C
L
= 100 pF, R
L
= 2 k
250
200
ns (max)
ns (max)
ns
t
1H
, t
0H
TRI-STATE Delay from Rising Edge
of CS to Data Output and SARS Hi-Z
50
180
ns (max)
pF
pF
pF
C
IN
C
IN
C
OUT
Capacitance of Analog Input (Note 17)
Capacitance of Logic Inputs
Capacitance of Logic Outputs
13
5
5
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