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參數(shù)資料
| 型號： | ADC0851BIV |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | ADC |
| 英文描述： | 8-Bit Analog Data Acquisition and Monitoring Systems |
| 中文描述： | 2-CH 8-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PQCC20 |
| 封裝： | PLASTIC, LCC-20 |
| 文件頁數(shù)： | 4/36頁 |
| 文件大小： | 581K |
| 代理商： | ADC0851BIV |
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DC Electrical Characteristics
(Continued)
The following specifications apply for V
CC
e a
5 V
DC
, V
REF
e a
4.5 V
DC
, AGND
e
DGND
e
0V and f
OSC
e
1 MHz (R
ext
e
3.16 k
X
, C
ext
e
170 pF) unless otherwise specified.
Boldface limits apply for T
A
e
T
J
e
T
MIN
to T
MAX
;
all other limits apply
at T
A
e
T
J
e a
25
§
C.
Parameter
Conditions
Typical
(Note 5)
Limit
(Note 6)
Units
(Limits)
DIGITAL CHARACTERISTICS
Logic ‘‘1’’ Input
Voltage, V
IH
V
CC
e
5.5V
2.2
V (Min)
Logic ‘‘0’’ Input
Voltage, V
IL
V
CC
e
4.5V
0.8
V(Max)
Logic ‘‘1’’ Input
Current, I
IH
V
IN
e
V
CC
0.005
3
m
A (Max)
Logic ‘‘0’’ Input
Current, I
IL
V
IN
e
0V
b
0.005
b
3
m
A (Max)
Logic ‘‘1’’ Output
Voltage, V
OH
(Except INT)
V
CC
e
4.5V
I
OUT
e b
360
m
A
I
OUT
e b
10
m
A
2.4
4.2
V (Min)
V (Min)
Logic ‘‘0’’ Output
Voltage, V
OL
TRI-STATE
é
Output
Current (DO)
I
OUT
e
1.6 mA
V
CC
e
4.5V
0.4
V (Max)
CS
e
Logic ‘‘1’’ (5V)
V
OUT
e
0.4V
V
OUT
e
5V
b
0.1
0.1
b
3
3
m
A (Max)
m
A (Max)
I
SOURCE
(Except INT)
V
OUT
Short to GND
b
14
b
6.5
mA (Min)
I
SINK
V
OUT
Short to V
CC
16
8
mA (Min)
Supply Current, I
CC
ADC0851 or ADC0858
f
CLK
e
1 MHz
f
CLK
e
2 MHz
(Note 10)
7
10
mA (Max)
mA
7.2
AC Electrical Characteristics
The following specifications apply for V
CC
e a
5 V
DC
, V
REF
e a
4.5 V
DC
, AGND
e
DGND
e
0V, f
CLK
e
1 MHz, t
r
e
t
f
e
5 ns unless otherwise specified.
Boldface limits apply for T
A
e
T
J
e
T
MIN
to T
MAX
;
all other limits apply at T
A
e
T
J
e
25
§
C.
Symbol
Parameter
Conditions
Typical
(Note 5)
Limit
(Note 6)
Units
(Limits)
f
CLK
Data Clock Frequency
1
2
MHz (Max)
Clock Duty Cycle
(Note 11)
40
60
% (Min)
% (Max)
t
SET-UP
CS Falling Edge or
Data Input Valid to
CLK Rising Edge
30
70
ns (Min)
t
HOLD
Data Input Valid after
CLK Rising Edge
5
30
ns (Min)
t
PD1
, t
PD0
CLK Rising Edge to
Output Data Valid
C
L
e
100 pF
80
200
ns (Max)
4
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