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參數(shù)資料
| 型號(hào)： | ADC0838CCV |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | ADC |
| 英文描述： | 8-Bit Serial I/O A/D Converters with Multiplexer Options |
| 中文描述： | 8-CH 8-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PQCC20 |
| 封裝： | PLASTIC, LCC-20 |
| 文件頁數(shù)： | 3/26頁 |
| 文件大小： | 410K |
| 代理商： | ADC0838CCV |
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ML2281, ML2282, ML2284, ML2288
3
NAME
FUNCTION
V
CC
DGND
Positive supply. 5V ± 10%
Digital ground. 0 volts. All digital inputs and
outputs are referenced to this point.
AGND
Analog ground. The negative reference voltage
for A/D converter.
CH0-7,
V
IN
+, V
IN
– ended (V
IN
) or; V
IN
+ or V
IN
– of a differential
input. Analog range = GND - V
IN
- V
CC
.
COM
Common reference point for analog inputs.
A/D conversion is performed on voltage
difference between analog input and this
common reference point if single-end
conversion is specified.
Analog inputs. Digitally selected to be single
V
REF
Reference. The positive reference voltage for
A/D converter.
SE
Shift enable. Input controls whether LSB first
bit stream is shifted out on serial output DO.
If
SE
= 1, MSB first is shifted out only. If
SE
= 0,
an MSB first bit stream is shifted out, then a
second bit stream with LSB first is shifted out
after end of conversion.
V+
Input to the Shunt Regulator.
PIN DESCRIPTION
NAME
FUNCTION
DO
Data out. Digital output which contains result
of A/D conversion. The serial data is clocked
out on falling edges of CLK.
SARS
Successive approximation register status.
Digital output which indicates that a
conversion is in progress. When SARS goes
to 1, the sampling window is closed and
conversion begins. When SARS goes to 0,
conversion is completed. When
CS
= 1, SARS
is in high impedance state.
CLK
Clock. Digital input which clocks data in on
DI on rising edges and out on DO on falling
edges. Also used to generate clocks for A/D
conversion.
DI
Data input. Digital input which contains serial
data to program the MUX and channel
assignments.
CS
Chip select. Selects the chip for multiplexer
and channel assignment and A/D conversion.
When
CS
= 1, all digital outputs are in high
impedance state. When
CS
= 0, normal A./D
conversion takes place.
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