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| 型號(hào)： | ADC082S101EVAL |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | 2 Channel, 1 MSPS, 8-Bit A/D Converter |
| 中文描述： | 2通道，1 MSPS的，8位A / D轉(zhuǎn)換器 |
| 文件頁(yè)數(shù)： | 4/19頁(yè) |
| 文件大小： | 925K |
| 代理商： | ADC082S101EVAL |
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ADC082S101 Converter Electrical Characteristics
(Note 9) (Continued)
The following specifications apply for V
= +2.7V to 5.25V, GND = 0V, f
SCLK
= 8 MHz to 16 MHz, f
= 500 kSPS to 1
MSPS, C
L
= 50 pF, unless otherwise noted.
Boldface limits apply for T
A
= T
MIN
to T
MAX
: all other limits T
A
= 25C.
Symbol
Parameter
Conditions
Typical
Limits
(Note 7)
Units
ANALOG INPUT CHARACTERISTICS
V
IN
Input Range
I
DCL
DC Leakage Current
0 to V
A
V
±
1
μA (max)
pF
pF
C
INA
Input Capacitance
Track Mode
Hold Mode
33
3
DIGITAL INPUT CHARACTERISTICS
V
IH
Input High Voltage
V
A
= +5.25V
V
A
= +3.6V
2.4
2.1
0.8
±
10
4
V (min)
V (min)
V (max)
μA (max)
pF (max)
V
IL
I
IN
C
IND
DIGITAL OUTPUT CHARACTERISTICS
Input Low Voltage
Input Current
Digital Input Capacitance
V
IN
= 0V or V
A
2
V
OH
Output High Voltage
I
SOURCE
= 200 μA
I
SOURCE
= 1mA
I
SINK
= 200 μA
I
SINK
= 1 mA
V
A
0.03
V
A
0.1
0.03
0.1
V
A
0.5
V (min)
V
V (max)
V
V
OL
Output Low Voltage
0.4
I
OZH
,
I
OZL
C
OUT
TRI-STATE
Leakage Current
±
0.01
±
1
μA (max)
TRI-STATE
Output Capacitance
Output Coding
POWER SUPPLY CHARACTERISTICS (C
L
= 10 pF)
2
4
pF (max)
Straight (Natural) Binary
V
A
Supply Voltage
2.7
5.25
V (min)
V (max)
I
A
Supply Current, Normal Mode
(Operational, CS low)
V
A
= +5.25V,
f
SAMPLE
= 1 MSPS, f
IN
= 40 kHz
V
A
= +3.6V,
f
SAMPLE
= 1 MSPS, f
IN
= 40 kHz
V
A
= +5.25V,
f
SAMPLE
= 0 kSPS
V
A
= +3.6V,
f
SAMPLE
= 0 kSPS
V
A
= +5.25V
V
A
= +3.6V
V
A
= +5.25V
V
A
= +3.6V
1.82
2.4
mA (max)
0.9
1.2
mA (max)
Supply Current, Shutdown (CS high)
200
nA
200
nA
P
D
Power Consumption, Normal Mode
(Operational, CS low)
9.6
3.2
0.35
0.12
12.6
4.3
mW (max)
mW (max)
μW
μW
Power Consumption, Shutdown (CS
high)
AC ELECTRICAL CHARACTERISTICS
f
SCLK
Clock Frequency
(Note 8)
8
16
500
1
13
30
70
3
MHz (min)
MHz (max)
kSPS (min)
MSPS (max)
SCLK cycles
% (min)
% (max)
SCLK cycles
f
S
Sample Rate
(Note 8)
t
CONV
Conversion Time
DC
SCLK Duty Cycle
f
SCLK
= 16 MHz
50
t
ACQ
Track/Hold Acquisition Time
Full-Scale Step Input
Acquisition Time + Conversion
Time
Throughput Time
16
SCLK cycles
A
www.national.com
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