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參數(shù)資料
| 型號： | ADC08161CIWM |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | ADC |
| 英文描述： | 500 ns A/D Converter with S/H Function and 2.5V Bandgap Reference |
| 中文描述： | 1-CH 8-BIT FLASH METHOD ADC, PARALLEL ACCESS, PDSO20 |
| 封裝： | SOP-20 |
| 文件頁數(shù)： | 4/15頁 |
| 文件大?。?/td> | 246K |
| 代理商： | ADC08161CIWM |
AC Electrical Characteristics
The following specifications apply for V
+
= 5V, t
= t
= 10 ns, V
REF+
= 5V, V
REF
= 0V unless otherwise specified.
Boldface
limits apply for T
A
= T
J
= T
MIN
to T
MAX
;
all other limits T
A
= T
J
Symbol
Parameter
Conditions
Typical
(Note 7)
100
Limit
(Note 8)
100
Units
(Limit)
ns (min)
t
WR
Write Time
Mode Pin to V
+
(Figures 2, 3, 4)
Mode Pin to V
+
, (Figure 2)
t
RD
Read Time (Time from Rising Edge
of WR to Falling Edge of RD )
RD Width
350
350
ns (min)
t
RDW
Mode Pin to GND (Figure 5 )
200
400
500
250
400
560
ns (min)
ns (max)
ns (max)
t
CONV
WR -RD Mode Conversion Time
(t
WR
+ t
RD
+ t
ACC1
)
RD Mode Conversion Time
Access Time (Delay from Falling
Edge of RD to Output Valid)
Access Time (Delay from
Falling Edge of RD
to Output Valid)
Mode Pin to V
+
, (Figure 2 )
t
CRD
t
ACCO
Mode Pin to GND, (Figure 1 )
C
L
≤
100 pF, Mode Pin to GND
(Figure 1 )
C
L
≤
10 pF
C
L
= 100 pF
Mode Pin to V
+
, t
RD
≤
t
INTL
(Figure 2 )
C
L
≤
10 pF
C
L
= 100 pF
t
RD
>
t
INTL
,
(Figures 3, 5)
R
L
= 3 k
, C
L
= 10 pF
(Figures 1, 2, 3, 4, 5)
655
640
900
900
ns (max)
ns (max)
t
ACC1
45
50
ns
110
ns (max)
t
ACC2
Access Time (Delay from
Falling Edge of RD
to Output Valid)
25
30
ns
55
ns (max)
t
1H
, t
0H
TRI-STATE
Control
(Delay from Rising Edge
of RD to HI-Z State)
Delay from Rising Edge of
WR to Falling Edge of INT
Delay from Rising Edge of
RD to Rising Edge of INT
Delay from Rising Edge of
WR to Rising Edge of INT
Delay from CS to RDY
30
60
ns (max)
t
INTL
Mode Pin = V
+
, C
L
= 50 pF
(Figures 3, 4)
C
L
= 50 pF,
(Figures 1, 2, 3, 5)
C
L
= 50 pF, (Figure 4)
520
690
ns (max)
t
INTH
50
95
ns (max)
t
INTH
45
95
ns (max)
t
RDY
Mode Pin = 0V, C
L
= 50 pF,
R
L
= 3 k
, (Figure 1)
R
L
= 3 k
, C
L
= 100 pF
(Figure 4)
Mode Pin = V
+
, t
RD
≤
t
INTL
(Figure 2)
(Figures 1, 2, 3, 4, 5)
25
45
ns (max)
t
ID
Delay from INT
to Output Valid
Delay from RD to INT
0
15
ns (max)
t
RI
60
115
ns (max)
t
N
Time between End of RD
and Start of New Conversion
CS Setup Time
CS Hold Time
50
50
ns (min)
t
CSS
t
CSH
(Figures 1, 2, 3, 4, 5)
(Figures 1, 2, 3, 4, 5)
0
0
0
0
ns (max)
ns (max)
DC Electrical Characteristics
The following specifications apply for V
= 5V unless otherwise specified.
Boldface limits apply for T
A
= T
J
= T
MIN
to T
MAX
;
all other limits T
A
= T
J
= 25C.
Symbol
Parameter
Conditions
Typical
(Note 7)
Limit
(Note 8)
Units
(Limit)
V
IH
Logic “1” Input Voltage
V
+
= 5.5 V
CS, WR, RD, A0, A1, A2 Pins
Mode Pin
2.0
3.5
V (min)
www.national.com
4
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| ADC08161CIWM/NOPB | 制造商:Texas Instruments 功能描述:ADC Single Pipelined 1.5Msps 8-bit Parallel 20-Pin SOIC W |
| ADC08161CIWMX | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog-to-Digital Converter， 8-Bit |
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| ADC08161CMJ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog-to-Digital Converter， 8-Bit |
| ADC08164BIJ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Single-Ended Data Acquisition System |
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