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| 型號： | ADC08134 |
| 廠商： | National Semiconductor Corporation |
| 元件分類： | 串行ADC |
| 英文描述： | 8-Bit High-Speed Serial I/O A/D Converters with Multiplexer Options, Voltage Reference, and Track/Hold Function(8位高速串行輸入/輸出A/D轉(zhuǎn)換器帶多路選擇，電壓基準(zhǔn)和跟蹤/保持功能) |
| 中文描述： | 8位高速串行I /辦公自動化/ D的多路復(fù)用器選項，電壓參考，并跟蹤轉(zhuǎn)換器/保持功能（8位高速串行輸入/輸出的A / D轉(zhuǎn)換器帶多路選擇，電壓基準(zhǔn)和跟蹤/保持功能） |
| 文件頁數(shù)： | 13/21頁 |
| 文件大?。?/td> | 483K |
| 代理商： | ADC08134 |
Functional Description
(Continued)
TABLE 3. MUX Addressing: ADC08138
(Continued)
Differential MUX Mode
MUX Address
SGL/
DIF
0
Analog Differential Channel-Pair
#
1
2
3
START
ODD/
SIGN
1
SELECT
1
1
0
2
3
0
1
0
1
4
5
6
7
+
1
TABLE 4. MUX Addressing: ADC08134
Single-Ended MUX Mode
MUX Address
SGL/
DIF
1
1
1
1
Channel
#
1
START
ODD/
SIGN
0
0
1
1
SELECT
1
0
1
0
1
0
2
3
1
1
1
1
+
+
+
+
COM is internally tied to AGND
Differential MUX Mode
MUX Address
SGL/
DIF
0
0
0
0
Channel
#
1
START
ODD/
SIGN
0
0
1
1
SELECT
1
0
1
0
1
0
2
3
1
1
1
1
+
+
+
+
Since the input configuration is under software control, it can
be modified as required before each conversion. A channel
can be treated as a single-ended, ground referenced input
for one conversion; then it can be reconfigured as part of a
differential channel for another conversion. Figure 1 illus-
trates the input flexibility which can be achieved.
The analog input voltages for each channel can range from
50 mV below ground to 50 mV above V
CC
(typically 5V)
without degrading conversion accuracy.
THE DIGITAL INTERFACE
A most important characteristic of these converters is their
serial data link with the controlling processor. Using a serial
communication format offers two very significant system
improvements; it allows many functions to be included in a
small package and it can eliminate the transmission of low
level analog signals by locating the converter right at the
analog sensor; transmitting highly noise immune digital data
back to the host processor.
To understand the operation of these converters it is best to
refer to the Timing Diagrams and Functional Block Diagram
and to follow a complete conversion sequence. For clarity a
separate timing diagram is shown for each device.
1.
A conversion is initiated by pulling the CS (chip select)
line low. This line must be held low for the entire con-
version. The converter is now waiting for a start bit and
its MUX assignment word.
2.
On each rising edge of the clock the status of the data in
(DI) line is clocked into the MUX address shift register.
The start bit is the first logic “1” that appears on this line
(all leading zeros are ignored). Following the start bit the
converter expects the next 2 to 4 bits to be the MUX
assignment word.
When the start bit has been shifted into the start location
of the MUX register, the input channel has been as-
signed and a conversion is about to begin. An interval of
1
2
clock period is automatically inserted to allow for
sampling the analog input. The SARS line goes high at
the end of this time to signal that a conversion is now in
progress and the DI line is disabled (it no longer accepts
data).
The data out (DO) line now comes out of TRI-STATE
and provides a leading zero.
During the conversion the output of the SAR comparator
indicates whether the analog input is greater than (high)
or less than (low) a series of successive voltages gen-
erated internally from a ratioed capacitor array (first 5
bits) and a resistor ladder (last 3 bits). After each com-
parison the comparator’s output is shipped to the DO
line on the falling edge of CLK. This data is the result of
the conversion being shifted out (with the MSB first) and
can be read by the processor immediately.
After 8 clock periods the conversion is completed. The
SARS line returns low to indicate this
1
2
clock cycle later.
3.
4.
5.
6.
A
www.national.com
13
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