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參數(shù)資料
| 型號(hào)： | ADC08100CIMTX |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | ADC |
| 英文描述： | 8-Bit, 20 MSPS to 100 MSPS, 1.3 mW/MSPS A/D Converter |
| 中文描述： | 1-CH 8-BIT RESISTANCE LADDER ADC, PARALLEL ACCESS, PDSO24 |
| 封裝： | TSSOP-24 |
| 文件頁(yè)數(shù)： | 3/19頁(yè) |
| 文件大小： | 572K |
| 代理商： | ADC08100CIMTX |
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Pin Descriptions and Equivalent Circuits
(Continued)
Pin No.
Symbol
Equivalent Circuit
Description
23
PD
Power Down input. When this pin is high, the converter is
in the Power Down mode and the data output pins hold
the last conversion result.
24
CLK
CMOS/TTL compatible digital clock Input. V
IN
is sampled
on the falling edge of CLK input.
13 thru 16
and
19 thru 22
D0–D7
Conversion data digital Output pins. D0 is the LSB, D7 is
the MSB. Valid data is output just after the rising edge of
the CLK input.
7
V
IN
GND
Reference ground for the single-ended analog input, V
IN
.
Positive analog supply pin. Connect to a clean, quiet
voltage source of +3V. V
A
should be bypassed with a
0.1 μF ceramic chip capacitor for each pin, plus one
10 μF capacitor. See Section 3.0 for more information.
Power supply for the output drivers. If connected to V
A
,
decouple well from V
A
.
The ground return for the output driver supply.
The ground return for the analog supply.
1, 4, 12
V
A
18
DR V
D
17
DR GND
AGND
2, 5, 8, 11
A
www.national.com
3
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