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參數(shù)資料
| 型號： | ADC0804LCN |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | ADC |
| 英文描述： | CMOS 8-bit A/D converters |
| 中文描述： | 1-CH 8-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, PDIP20 |
| 封裝： | 0.300 INCH, PLASTIC, DIP-20 |
| 文件頁數(shù)： | 7/18頁 |
| 文件大小： | 150K |
| 代理商： | ADC0804LCN |
Philips Semiconductors
Product data
ADC0803/0804
CMOS 8-bit A/D converters
2002 Oct 17
7
Full Scale Adjustment
Full scale gain is adjusted by applying any desired offset voltage to
V
IN
(–), then applying the V
IN
(+) a voltage that is 1-
1
/
2
LSB less than
the desired analog full-scale voltage range and then adjusting the
magnitude of V
REF
/2 input voltage (or the V
CC
supply if there is no
V
REF
/2 input connection) for a digital output code which just
changes from 1111 1110 to 1111 1111. The ideal V
IN
(+) voltage for
this full-scale adjustment is given by:
V
IN
(
)
V
IN
(
)
1.5 x
V
MAX
V
MIN
255
where:
V
MAX
= high end of analog input range (ground referenced)
V
MIN
= low end (zero offset) of analog input (ground referenced)
CLOCKING OPTION
The clock signal for these A/Ds can be derived from external
sources, such as a system clock, or self-clocking can be
accomplished by adding an external resistor and capacitor, as
shown in Figure 11.
Heavy capacitive or DC loading of the CLK R pin should be avoided
as this will disturb normal converter operation. Loads less than 50pF
are allowed. This permits driving up to seven A/D converter CLK IN
pins of this family from a single CLK R pin of one converter. For
larger loading of the clock line, a CMOS or low power TTL buffer or
PNP input logic should be used to minimize the loading on the CLK
R pin.
Restart During a Conversion
A conversion in process can be halted and a new conversion began
by bringing the CS and WR inputs low and allowing at least one of
them to go high again. The output data latch is not updated if the
conversion in progress is not completed; the data from the
previously completed conversion will remain in the output data
latches until a subsequent conversion is completed.
Continuous Conversion
To provide continuous conversion of input data, the CS and RD
inputs are grounded and INTR output is tied to the WR input. This
INTR/WR connection should be momentarily forced to a logic low
upon power-up to insure circuit operation. See Figure 10 for one
way to accomplish this.
DRIVING THE DATA BUS
This CMOS A/D converter, like MOS microprocessors and
memories, will require a bus driver when the total capacitance of the
data bus gets large. Other circuitry tied to the data bus will add to
the total capacitive loading, even in the high impedance mode.
There are alternatives in handling this problem. The capacitive
loading of the data bus slows down the response time, although DC
specifications are still met. For systems with a relatively low CPU
clock frequency, more time is available in which to establish proper
logic levels on the bus, allowing higher capacitive loads to be driven
(see Typical Performance Characteristics).
At higher CPU clock frequencies, time can be extended for I/O
reads (and/or writes) by inserting wait states (8880) or using
clock-extending circuits (6800, 8035).
Finally, if time is critical and capacitive loading is high, external bus
drivers must be used. These can be 3-State buffers (low power
Schottky is recommended, such as the N74LS240 series) or special
higher current drive products designed as bus drivers. High current
bipolar bus drivers with PNP inputs are recommended as the PNP
input offers low loading of the A/D output, allowing better response
time.
POWER SUPPLIES
Noise spikes on the V
CC
line can cause conversion errors as the
internal comparator will respond to them. A low inductance filter
capacitor should be used close to the converter V
CC
pin and values
of 1
μ
F or greater are recommended. A separate 5 V regulator for
the converter (and other 5 V linear circuitry) will greatly reduce
digital noise on the V
CC
supply and the attendant problems.
WIRING AND LAYOUT PRECAUTIONS
Digital wire-wrap sockets and connections are not satisfactory for
breadboarding this (or any) A/D converter. Sockets on PC boards
can be used. All logic signal wires and leads should be grouped or
kept as far as possible from the analog signal leads. Single wire
analog input leads may pick up undesired hum and noise, requiring
the use of shielded leads to the analog inputs in many applications.
A single-point analog ground separate from the logic or digital
ground points should be used. The power supply bypass capacitor
and the self-clocking capacitor, if used, should be returned to digital
ground. Any V
REF
/2 bypass capacitor, analog input filter capacitors,
and any input shielding should be returned to the analog ground
point. Proper grounding will minimize zero-scale errors which are
present in every code. Zero-scale errors can usually be traced to
improper board layout and wiring.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| ADC0804LCN | 制造商:Texas Instruments 功能描述:IC 8BIT ADC DIP20 804 |
| ADC0804LCN/A+ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog-to-Digital Converter， 8-Bit |
| ADC0804LCN/B+ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog-to-Digital Converter， 8-Bit |
| ADC0804LCN/NOPB | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 8B UP COMPATIBLE ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結構:Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADC0804LCN/NOPB | 制造商:Texas Instruments 功能描述:A/D Converter (A-D) IC |
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