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參數(shù)資料
| 型號： | ADC08038CIN |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | ADC |
| 英文描述： | 8-Bit High-Speed Serial I/O A/D Converters with Multiplexer Options, Voltage Reference, and Track/Hold Function |
| 中文描述： | 8-CH 8-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDIP20 |
| 封裝： | 0.300 INCH, DIP-20 |
| 文件頁數(shù)： | 12/24頁 |
| 文件大?。?/td> | 552K |
| 代理商： | ADC08038CIN |
Functional Description
(Continued)
TABLE 4. MUX Addressing: ADC08034
Single-Ended MUX Mode
MUX Address
SGL/
DIF
1
1
1
1
Channel
#
1
START
ODD/
SIGN
0
0
1
1
SELECT
1
0
1
0
1
0
2
3
1
1
1
1
+
+
+
+
COM is internally tied to AGND
MUX Addressing:
ADC08032
Single-Ended MUX Mode
MUX Address
START
SGL/
DIF
1
1
1
1
Channel
#
0
ODD/
SIGN
0
1
1
+
+
COM is internally tied to AGND
Differential MUX Mode
MUX Address
SGL/
DIF
0
0
0
0
Channel
#
1
START
ODD/
SIGN
0
0
1
1
SELECT
1
0
1
0
1
0
2
3
1
1
1
1
+
+
+
+
Differential MUX Mode
MUX Address
START
SGL/
DIF
1
1
Channel
#
0
ODD/
SIGN
0
1
1
0
0
+
+
Since the input configuration is under software control, it can
be modified as required before each conversion. A channel
can be treated as a single-ended, ground referenced input
for one conversion; then it can be reconfigured as part of a
differential channel for another conversion. Figure 1 illus-
trates the input flexibility which can be achieved.
The analog input voltages for each channel can range from
50mV below ground to 50mV above V
CC
(typically 5V) with-
out degrading conversion accuracy.
2.0 THE DIGITAL INTERFACE
A most important characteristic of these converters is their
serial data link with the controlling processor. Using a serial
communication format offers two very significant system im-
provements; it allows many functions to be included in a
small package and it can eliminate the transmission of low
level analog signals by locating the converter right at the
analog sensor; transmitting highly noise immune digital data
back to the host processor.
To understand the operation of these converters it is best to
refer to the Timing Diagrams and Functional Block Diagram
and to follow a complete conversion sequence. For clarity a
separate timing diagram is shown for each device.
1.
A conversion is initiated by pulling the CS (chip select)
line low. This line must be held low for the entire conver-
sion. The converter is now waiting for a start bit and its
MUX assignment word.
2.
On each rising edge of the clock the status of the data in
(DI) line is clocked into the MUX address shift register.
The start bit is the first logic “1” that appears on this line
(all leading zeros are ignored). Following the start bit the
converter expects the next 2 to 4 bits to be the MUX as-
signment word.
A
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