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參數(shù)資料
| 型號： | ADC0802LCWM |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | ADC |
| 英文描述： | 8-Bit uP Compatible A/D Converters |
| 中文描述： | 1-CH 8-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, PDSO20 |
| 封裝： | SOIC-20 |
| 文件頁數(shù)： | 19/41頁 |
| 文件大?。?/td> | 1118K |
| 代理商： | ADC0802LCWM |
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Functional Description
(Continued)
After the “1” is clocked through the 8-bit shift register (which
completes the SAR search) it appears as the input to the
D-type latch, LATCH 1. As soon as this “1” is output from the
shift register, the AND gate, G2, causes the new digital word
to transfer to the TRI-STATE output latches. When LATCH 1
is subsequently enabled, the Q output makes a high-to-low
transition which causes the INTR F/F to set. An inverting
buffer then supplies the INTR input signal.
Note that this SET control of the INTR F/F remains low for 8
of the external clock periods (as the internal clocks run at
1
8
of the frequency of the external clock). If the data output is
continuously enabled (CS and RD both held low), the INTR
output will still signal the end of conversion (by a high-to-low
transition), because the SET input can control the Q output
of the INTR F/F even though the RESET input is constantly
at a “1” level in this operating mode. This INTR output will
therefore stay low for the duration of the SET signal, which is
8 periods of the external clock frequency (assuming the A/D
is not started during this interval).
When operating in the free-running or continuous conversion
mode (INTR pin tied to WR and CS wired low— see also
section 2.8), the START F/F is SET by the high-to-low tran-
sition of the INTR signal. This resets the SHIFT REGISTER
which causes the input to the D-type latch, LATCH 1, to go
low.As the latch enable input is still present, the Q output will
go high, which then allows the INTR F/F to be RESET. This
reduces the width of the resulting INTR output pulse to only
a few propagation delays (approximately 300 ns).
When data is to be read, the combination of both CS and RD
being low will cause the INTR F/F to be reset and the
TRI-STATE output latches will be enabled to provide the 8-bit
digital outputs.
2.1 Digital Control Inputs
The digital control inputs (CS, RD, and WR) meet standard
T
2
L logic voltage levels. These signals have been renamed
when compared to the standardA/D Start and Output Enable
labels. In addition, these inputs are active low to allow an
easy interface to microprocessor control busses. For
non-microprocessor based applications, the CS input (pin 1)
can be grounded and the standard A/D Start function is ob-
tained by an active low pulse applied at the WR input (pin 3)
and the Output Enable function is caused by an active low
pulse at the RD input (pin 2).
DS005671-13
Note 13:
CS shown twice for clarity.
Note 14:
SAR = Successive Approximation Register.
FIGURE 4. Block Diagram
A
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| ADC0802LCWM/NOPB | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 8B uP Compatible ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
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| ADC0802LCWMX/NOPB | 功能描述:IC ADC 8BIT MPU COMPAT 20-SOIC RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:- 位數(shù):12 采樣率（每秒）:3M 數(shù)據(jù)接口:- 轉(zhuǎn)換器數(shù)目:- 功率耗散（最大）:- 電壓電源:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:SOT-23-6 供應(yīng)商設(shè)備封裝:SOT-23-6 包裝:帶卷 (TR) 輸入數(shù)目和類型:- |
| ADC0802LD | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:8-Bit, Microprocessor- Compatible, A/D Converters |
| ADC0802LJ | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:8-Bit uP Compatible A/D Converters |
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