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參數(shù)資料
| 型號： | ADC_PCI2010_CS2 |
| 英文描述： | ADC_PCI2010_CS2 8-BIT 250KSPS SAR ADC|Data Sheet |
| 中文描述： | ADC_PCI2010_CS2 8位250ksps的SAR型ADC |數(shù)據(jù)資料 |
| 文件頁數(shù)： | 1/10頁 |
| 文件大小： | 86K |
| 代理商： | ADC_PCI2010_CS2 |
SEC ASIC
ANALOG
GENERAL
DESCRIPTION
The adc_pci2010_cs2 is a CMOS 8-bit low supply, low
power, successive approximation A/D converter which is
composed of auto-zeroing comparator, 8-bit DAC, clock
generator,
successive
approximation
output register. The 8-bit DAC consists of capacitor
arrays and resistor strings. The conversion result can be
accessed over a parallel interface. The adc_pci2010_cs2
operates with a single +2.5V power supply and the
conversion rate is up to 250KSPS.
register(SAR)
and
FEATURES
- Resolution: 8-Bit
- Differential Linearity Error:±0.5 LSB(Max)
- Integral Linearity Error:±0.75 LSB(Typ)
- Maximum Conversion Rate: 250KSPS
- Low Power Consumption: 2.5mW(Typ)
- Power Supply Voltage: 2.5V(Typ)
- No Pipeline Delays
- No Missing Code Guaranteed
- Internal Voltage Reference
- Operating Temperature Range: -40oC~85oC
8-BIT 250KSPS SAR ADC
ADC_PCI2010_CS2
Ver 1.0 (July, 2000)
This data sheet is a preliminary version. No responsibility is assumed by SEC for its
use nor for any infringements of patents or other rights of third parties that may result
from its use. The content of this data sheet is subject to change without any notice.
FUNCTIONAL BLOCK DIAGRAM
CLK
SLEEP
EOC
AVSS25A
AVDD25A
A1
VCOM
REFB
AVSS25D
AVDD25D
AVBBD
DO[7:0]
CONV
REFT
AVBBA
AVDD25O AVSS25O
INP[7:0]
INN
8-Bit DAC
COMP
CONTROLLER
OUT_REG
SAR
MUX
(8:1)
MCO[2:0]
AVDD18D
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