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| 型號(hào)： | ADAU1592ACPZ-RL |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 10/24頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC AMP AUDIO PWR 24W 48LFCSP |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 類型： | D 類 |
| 輸出類型： | 2 通道（立體聲） |
| 在某負(fù)載時(shí)最大輸出功率 x 通道數(shù)量： | 24W x 2 @ 4 歐姆 |
| 電源電壓： | 9 V ~ 18 V |
| 特點(diǎn)： | 消除爆音，靜音，短路和熱保護(hù)，待機(jī) |
| 安裝類型： | 表面貼裝 |
| 供應(yīng)商設(shè)備封裝： | 48-LFCSP-VQ（7x7） |
| 封裝/外殼： | 48-VFQFN 裸露焊盤，CSP |
| 包裝： | 帶卷 (TR) |
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ADAU1592
Rev. A | Page 18 of 24
POWER-UP/POWER-DOWN SEQUENCE
Figure 46 shows the recommended power-up sequence for the
ADAU1592.
06
74
9-
0
46
AVDD/DVDD
PVDD
STDN
MUTE
OUTx+/OUTx–
PVDD/2
AINx
AVDD/2
tPDL-H
tINT
tWAIT
tINT = 650ms @ 24.576MHz CLOCK
tPDL-H = 200s
tWAIT = 10 × RIN × CIN
INTERNAL MUTE
NOTES
1. INTERNAL MUTE IS INTERNAL TO CHIP.
Figure 46. Recommended Power-Up Sequence
The ADAU1592 has a special power-up sequence that consists
of a fixed internal mute time during which the power stage does
not start switching. This internal mute time depends on the
master clock frequency and is 650 ms for a 24.576 MHz clock.
Also, the internal mute overrides the external MUTE and
ensures that the power stage does not switch on immediately
even if the external MUTE signal is pulled high in less than
650 ms after STDN. The power stage starts switching only after
650 ms plus a small propagation delay of 200 μs have elapsed
and after MUTE is deasserted. Therefore, it is recommended to
ensure that tWAIT > tINT to prevent the pop and click during
power-up.
Ensure that the MUTE signal is delayed by at least tWAIT
seconds after STDN. This time is approximately 10 times the
charging time constant of the input coupling capacitor.
For example, if the input coupling capacitor is 4.7 μF, the time
constant is
T = R × C = 20 kΩ × 4.7 μF = 94 ms
Therefore, tWAIT = 10 × T = 940 ms ~ 1 sec.
tWAIT is needed to ensure that the input capacitors are charged to
AVDD/2 before turning on the power stage.
When tWAIT < tINT, the power stage does not start switching until
650 ms have elapsed after STDN (see Figure 47). However, note
that this method does not ensure pop-and-click suppression
because of less than recommended or insufficient tWAIT.
tINT = 650ms @ 24.576MHz CLOCK
tWAIT < tINT
06
74
9-
04
7
AVDD/DVDD
PVDD
STDN
MUTE
OUTx+/OUTx–
PVDD/2
AINx
AVDD/2
tINT
tWAIT
INTERNAL MUTE
NOTES
1. INTERNAL MUTE IS INTERNAL TO CHIP.
Figure 47. Power-Up Sequence, tWAIT < tINT
The ADAU1592 uses three separate supplies: AVDD (3.3 V
analog for PGA and modulator), DVDD (3.3 V digital for
control logic and clock oscillator), and PVDD (9 V to 18 V
power stage and level shifter). Separate pins are provided for
the AVDD, DVDD, and PVDD supply connections, as well as
AGND, DGND, and PGND.
In addition, the ADAU1592 incorporates a built-in undervolt-
age lockout logic on DVDD as well as PVDD. This helps detect
undervoltage operation and eliminates the need to have an external
mechanism to sense the supplies.
The ADAU1592 monitors the DVDD and PVDD supply voltages
and prevents the power stage from turning on if either of the
supplies is not present or is below the operating threshold.
Therefore, if DVDD is missing or below the operating thresh-
old, for example, the power stage does not turn on, even if
PVDD is present, or vice versa.
Because this protection is only present on DVDD and PVDD
and not on AVDD, shorting both AVDD and DVDD externally
or generating AVDD and DVDD from one power source is
recommended. This ensures that both AVDD and DVDD
supplies are tracking each other and avoids the need to monitor
the sequence with respect to PVDD. This also ensures minimal
pop and click during power-up.
When using separate AVDD and DVDD supplies, ensure that
both supplies are stable before unmuting or turning on the
power stage.
Similarly, during shutdown, pulling MUTE to logic low before
pulling STDN down is recommended. However, where a fault
event occurs, the power stage shuts down to protect the part. In
this case, depending on the signal level, there is some pop at the
speaker.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADAU1592ACPZ-RL7 | 功能描述:IC AMP AUDIO PWR 48LFCSP RoHS:是 類別:集成電路 (IC) >> 線性 - 音頻放大器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:DirectDrive® 類型:D 類 輸出類型:1-通道（單聲道），帶立體聲耳機(jī) 在某負(fù)載時(shí)最大輸出功率 x 通道數(shù)量:930mW x 1 @ 8 歐姆; 40mW x 2 @ 16 歐姆 電源電壓:2.7 V ~ 5.5 V 特點(diǎn):消除爆音，差分輸入，I²C，靜音，關(guān)閉，音量控制 安裝類型:表面貼裝 供應(yīng)商設(shè)備封裝:25-WLP（2.09x2.09） 封裝/外殼:25-WFBGA，WLCSP 包裝:帶卷 (TR) 其它名稱:MAX97000EWA+T-ND |
| ADAU1592ASVZ | 制造商:Analog Devices 功能描述:AMP AUDIO CLASS D SMD TQFPEP-48 |
| ADAU1592ASVZ-RL | 制造商:Analog Devices 功能描述: |
| ADAU1592ASVZ-RL7 | 制造商:Analog Devices 功能描述: |
| ADAU1701 | 制造商:AD 制造商全稱:Analog Devices 功能描述:SigmaDSP 28/56-Bit Audio Processor with 2ADC/4DAC |
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