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參數(shù)資料
| 型號： | ADA4941-1 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 16-Bit, +/-0.65 LSB INL, 500 kSPS PulSAR Differential ADC in MSOP/QFN |
| 中文描述： | 16位/ -0.65 LSB INL和500 kSPS的PulSAR系列差分ADC，采用MSOP / QFN封裝 |
| 文件頁數(shù)： | 17/24頁 |
| 文件大小： | 449K |
| 代理商： | ADA4941-1 |
Preliminary Technical Data
AD7693
CS MODE 3-WIRE, NO BUSY INDICATOR
Rev. PrB | Page 17 of 24
This mode is usually used when a single AD7693 is connected
to an SPI-compatible digital host. The connection diagram is
shown in Figure 33, and the corresponding timing is given in
Figure 34.
With SDI tied to VIO, a rising edge on CNV initiates a
conversion, selects the CS mode, and forces SDO to high
impedance. Once a conversion is initiated, it continues until
completion irrespective of the state of CNV. This could be
useful, for instance, to bring CNV low to select other SPI
devices, such as analog multiplexers; however, CNV must be
returned high before the minimum conversion time elapses and
then held high for the maximum possible conversion time to
avoid the generation of the busy signal indicator. When the
conversion is complete, the AD7693 enters the acquisition
phase and powers down. When CNV goes low, the MSB is
output onto SDO. The remaining data bits are clocked by
subsequent SCK falling edges. The data is valid on both SCK
edges. Although the rising edge can be used to capture the data,
a digital host using the SCK falling edge will allow a faster
reading rate, provided it has an acceptable hold time. After the
16
th
SCK falling edge, or when CNV goes high, whichever is
earlier, SDO returns to high impedance.
CNV
SCK
SDO
SDI
DATA IN
CLK
CONVERT
VIO
DIGITAL HOST
AD7693
-
CS
Figure 33. 3-Wire
Mode Without Busy Indicator
Connection Diagram (SDI High)
SDO
D15
D14
D13
D1
D0
t
DIS
SCK
1
2
3
14
15
16
t
SCK
t
SCKL
t
SCKH
t
HSDO
t
DSDO
CNV
CONVERSION
ACQUISITION
t
CONV
t
CYC
ACQUISITION
SDI = 1
t
CNVH
t
ACQ
t
EN
0
CS
Figure 34. 3-Wire
Mode Without Busy Indicator Serial Interface Timing (SDI High)
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