參數(shù)資料
型號: ADA4932-2YCPZ-R2
廠商: Analog Devices Inc
文件頁數(shù): 28/29頁
文件大小: 0K
描述: IC AMP DIFF DUAL LP 80MA 24LFCSP
特色產(chǎn)品: ADA4932-x Low Power Differential ADC Driver
標(biāo)準(zhǔn)包裝: 1
放大器類型: 差分
電路數(shù): 2
輸出類型: 差分
轉(zhuǎn)換速率: 2800 V/µs
-3db帶寬: 560MHz
電流 - 輸入偏壓: 2.5µA
電壓 - 輸入偏移: 500µV
電流 - 電源: 9.6mA
電流 - 輸出 / 通道: 80mA
電壓 - 電源,單路/雙路(±): 3 V ~ 11 V,±1.5 V ~ 5.5 V
工作溫度: -40°C ~ 105°C
安裝類型: 表面貼裝
封裝/外殼: 24-VFQFN 裸露焊盤,CSP
供應(yīng)商設(shè)備封裝: 24-LFCSP-VQ(4x4)
包裝: 標(biāo)準(zhǔn)包裝
產(chǎn)品目錄頁面: 765 (CN2011-ZH PDF)
其它名稱: ADA4932-2YCPZ-R2DKR
Data Sheet
ADA4932-1/ADA4932-2
ABSOLUTE MAXIMUM RATINGS
Table 7.
Parameter
Rating
Supply Voltage
11 V
Power Dissipation
Input Current, +IN, IN, PD
±5 mA
Storage Temperature Range
65°C to +125°C
Operating Temperature Range
40°C to +105°C
40°C to +105°C
Lead Temperature (Soldering, 10 sec)
300°C
Junction Temperature
150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational section of
this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device
reliability.
THERMAL RESISTANCE
θJA is specified for the device (including exposed pad) soldered
to a high thermal conductivity 2s2p circuit board, as described
in EIA/JESD 51-7.
Table 8. Thermal Resistance
Package Type
θJA
Unit
ADA4932-1, 16-Lead LFCSP (Exposed Pad)
91
°C/W
ADA4932-2, 24-Lead LFCSP (Exposed Pad)
65
°C/W
MAXIMUM POWER DISSIPATION
The maximum safe power dissipation in the ADA4932-x
package is limited by the associated rise in junction temperature
(TJ) on the die. At approximately 150°C, which is the glass
transition temperature, the plastic changes its properties. Even
temporarily exceeding this temperature limit can change the
stresses that the package exerts on the die, permanently shifting
the parametric performance of the ADA4932-x. Exceeding a
junction temperature of 150°C for an extended period can result
in changes in the silicon devices, potentially causing failure.
The power dissipated in the package (PD) is the sum of the
quiescent power dissipation and the power dissipated in the
package due to the load drive. The quiescent power is the voltage
between the supply pins (VS) times the quiescent current (IS).
The power dissipated due to the load drive depends upon the
particular application. The power due to load drive is calculated
by multiplying the load current by the associated voltage drop
across the device. RMS voltages and currents must be used in
these calculations.
Airflow increases heat dissipation, effectively reducing θJA. In
addition, more metal directly in contact with the package leads/
exposed pad from metal traces, through holes, ground, and power
planes reduces θJA.
Figure 4 shows the maximum safe power dissipation in the
package vs. the ambient temperature for the single 16-lead
LFCSP (91°C/W) and the dual 24-lead LFCSP (65°C/W) on a
JEDEC standard 4-layer board with the exposed pad soldered to
a PCB pad that is connected to a solid plane.
3.5
0
0.5
1.0
1.5
2.0
2.5
3.0
–40
100
80
60
40
20
0
–20
MA
XI
MU
M
PO
W
ER
D
ISSI
PA
T
IO
N
(W
)
AMBIENT TEMPERATURE (°C)
ADA4932-1
ADA4932-2
07752-
204
Figure 4. Maximum Power Dissipation vs. Ambient Temperature for
a 4-Layer Board
ESD CAUTION
Rev. C | Page 7 of 28
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