參數(shù)資料
型號(hào): ADA4850-2YCPZ-R2
廠商: Analog Devices Inc
文件頁數(shù): 14/17頁
文件大?。?/td> 0K
描述: IC OPAMP VF R-R DUAL 16LFCSP
標(biāo)準(zhǔn)包裝: 1
放大器類型: 電壓反饋
電路數(shù): 2
輸出類型: 滿擺幅
轉(zhuǎn)換速率: 220 V/µs
-3db帶寬: 175MHz
電流 - 輸入偏壓: 2.3µA
電壓 - 輸入偏移: 600µV
電流 - 電源: 2.5mA
電流 - 輸出 / 通道: 118mA
電壓 - 電源,單路/雙路(±): 2.7 V ~ 6 V
工作溫度: -40°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 16-VFQFN 裸露焊盤,CSP
供應(yīng)商設(shè)備封裝: 16-LFCSP-VQ
包裝: 標(biāo)準(zhǔn)包裝
產(chǎn)品目錄頁面: 770 (CN2011-ZH PDF)
其它名稱: ADA4850-2YCPZ-R2DKR
Data Sheet
ADA4850-1/ADA4850-2
Rev. C | Page 5 of 16
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter
Rating
Supply Voltage
12.6 V
Power Dissipation
Power Down Pin Voltage
(V
S + 6) V
Common-Mode Input Voltage
(V
S 0.5 ) V to (+VS + 0.5) V
Differential Input Voltage
+V
S to VS
Storage Temperature
65°C to +125°C
Operating Temperature Range
40°C to +125°C
Lead Temperature Range
(Soldering 10 sec)
300°C
Junction Temperature
150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, θJA is
specified for the device soldered in the circuit board for
surface-mount packages.
Table 4.
Package Type
θ
JA
Unit
16-Lead LFCSP
72.8
°C/W
8-Lead LFCSP
80
°C/W
Maximum Power Dissipation
The maximum safe power dissipation for the ADA4850-1/
ADA4850-2 is limited by the associated rise in junction
temperature (TJ) on the die. At approximately 150°C, which
is the glass transition temperature, the plastic changes its
properties. Even temporarily exceeding this temperature limit
may change the stresses that the package exerts on the die,
permanently shifting the parametric performance of the
ADA4850-1/ADA4850-2. Exceeding a junction temperature
of 150°C for an extended period of time can result in changes
in silicon devices, potentially causing degradation or loss of
functionality.
The power dissipated in the package (PD) is the sum of the quies-
cent power dissipation and the power dissipated in the die due
to the ADA4850-1/ADA4850-2 drive at the output. The
quiescent power is the voltage between the supply pins (VS)
times the quiescent current (IS).
PD = Quiescent Power + (Total Drive Power Load Power)
(
)
L
OUT
L
OUT
S
D
R
V
R
V
I
V
P
2
×
+
×
=
RMS output voltages should be considered. If RL is referenced
to VS, as in single-supply operation, the total drive power is
VS × IOUT. If the rms signal levels are indeterminate, consider
the worst case, when VOUT = VS/4 for RL to midsupply.
(
) ( )
L
S
D
R
4
V
I
V
P
2
/
+
×
=
In single-supply operation with RL referenced to VS, the worst
case is VOUT = VS/2.
Airflow increases heat dissipation, effectively reducing θJA.
Also, more metal directly in contact with the package leads and
exposed paddle from metal traces through holes, ground, and
power planes reduce θJA.
Figure 4 shows the maximum safe power dissipation in the
package vs. the ambient temperature for the LFCSP (91°C/W)
package on a JEDEC standard 4-layer board. θJA values are
approximations.
Figure 4. Maximum Power Dissipation vs. Temperature for a 4-Layer Board
ESD CAUTION
–55
125
–45 –35 –25 –15 –5
5
15 25 35 45 55 65 75 85 95 105 115
MA
XI
MU
M
PO
W
ER
D
ISSI
PA
T
IO
N
(W
)
AMBIENT TEMPERATURE (
°C)
05320-
055
0
3.0
2.5
2.0
1.5
1.0
0.5
LFCSP-8
LFCSP-16
TJ = 150°C
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