參數(shù)資料
型號(hào): ADA4062-4ACPZ-R7
廠商: Analog Devices Inc
文件頁(yè)數(shù): 8/20頁(yè)
文件大?。?/td> 0K
描述: IC OPAMP JFET 1.4MHZ QD 16LFCSP
標(biāo)準(zhǔn)包裝: 1,500
放大器類型: J-FET
電路數(shù): 4
轉(zhuǎn)換速率: 3.3 V/µs
增益帶寬積: 1.4MHz
電流 - 輸入偏壓: 2pA
電壓 - 輸入偏移: 750µV
電流 - 電源: 165µA
電流 - 輸出 / 通道: 20mA
電壓 - 電源,單路/雙路(±): 8 V ~ 36 V,±4 V ~ 18 V
工作溫度: -40°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 16-WFQFN 裸露焊盤,CSP
供應(yīng)商設(shè)備封裝: 16-LFCSP-WQ(3x3)
包裝: 帶卷 (TR)
ADA4062-2/ADA4062-4
Rev. B | Page 16 of 20
PHASE REVERSAL
Phase reversal occurs in some amplifiers when the input common-
mode voltage range is exceeded. When the voltage driving the
input to these amplifiers exceeds the maximum input common-
mode voltage range, the output of the amplifiers changes polarity.
Most JFET input amplifiers have phase reversal if either input
exceeds the input common-mode range.
For the ADA4062-x, the output does not phase reverse if one
or both of the inputs exceeds the input voltage range but remains
within the positive supply rail and 0.5 V above the negative
supply rail. In other words, for an application with a supply
voltage of ±15 V, the input voltage can be as high as +15 V
without any output phase reversal. However, when the voltage
of the inputs is driven beyond 14.5 V, phase reversal occurs
due to saturation of the input stage leading to forward biasing
of the gate-drain diode. Phase reversal in ADA4062-x can be
prevented by using a Schottky diode to clamp the input terminals
to each other. In the simple buffer circuit in Figure 63, D1
protects the op amp against phase reversal, and R limits the
input current that flows into the op amp.
+VSY
–VSY
VO
07
67
0-
05
3
R
10k
ADA4062-x
D1
IN5711
Figure 63. Phase Reversal Solution Circuit
07
67
0-
0
63
TIME (40s/DIV)
VO
LT
AG
E
(
5V
/DI
V
)
VSY = ±15V
VOUT
VIN
Figure 64. No Phase Reversal
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