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參數(shù)資料
| 型號： | AD995PCBZ |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 1 GSPS Quadrature Digital Upconverter w/18-Bit IQ Data Path and 14-Bit DAC |
| 中文描述： | 1 GSPS的正交數(shù)字上變頻器w/18-Bit智商數(shù)據(jù)路徑和14位DAC |
| 文件頁數(shù)： | 5/38頁 |
| 文件大?。?/td> | 602K |
| 代理商： | AD995PCBZ |
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PRELIMINARY TECHNICAL DATA
AD9957
Rev. PrF | Page 5 of 38
Parameter
Min
Typ
Max
Unit
CMOS LOGIC OUTPUTS (1 mA Load)
Logic 1 Voltage
Logic 0 Voltage
XTAL OUTPUT BUFFER SPECS
Logic 1 Voltage
Logic 0 Voltage
Output Current
POWER CONSUMPTION
DVDD_I/O(3.3V) current consumption (QDUC mode)
DVDD(1.8V) current consumption (QDUC mode)
AVDD(3.3V) current consumption (QDUC mode)
AVDD(1.8V) current consumption (QDUC mode)
Single Tone Mode
Continuous Modulation 255x Interpolation
Continuous Modulation 4x Interpolation
Burst Modulation (25%) 255x Interpolation
Burst Modulation (25%) 4x Interpolation
Full-Sleep Mode
Inverse Sinc Filter Power Consumption
2.8
1.6
500
TBD
TBD
TBD
TBD
TBD
150
0.4
TBD
TBD
1000
TBD
TBD
TBD
TBD
TBD
V
V
V
V
mA
mA
mA
mA
mA
mW
mW
mW
mW
mW
mW
mW
1 To achieve the best possible phase noise, the largest amplitude clock possible should be used. Reducing the clock input amplitude will
reduce the phase noise performance of the device.
2 Wake-up time refers to the recovery from analog power-down modes.
3 SYSCLK cycle refers to the actual clock frequency used on-chip by the DDS. If the reference clock multiplier is used to multiply the ex-
ternal reference clock frequency, the SYSCLK frequency is the external frequency multiplied by the reference clock multiplication factor.
If the reference clock multiplier and divider are not used, the SYSCLK frequency is the same as the external reference clock frequency.
Figure 2 Equivalent Input/Output (I/O) Circuits
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| AD9960BSTZ | 功能描述:RFID應(yīng)答器 MxFE for RFID Reader Transceiver RoHS:否 制造商:Murata 存儲容量:512 bit 工作溫度范圍:- 40 C to + 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體: 封裝:Reel |
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