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參數(shù)資料
| 型號： | AD9957BSVZREEL13 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | 1 GSPS Quadrature Digital Upconverter w/18-Bit IQ Data Path and 14-Bit DAC |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, QFP48 |
| 封裝： | PLASTIC, MS-026-AED-HD, TQFP-48 |
| 文件頁數(shù)： | 8/38頁 |
| 文件大?。?/td> | 602K |
| 代理商： | AD9957BSVZREEL13 |
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AD9957
PRELIMINARY TECHNICAL DATA
Rev. PrF | Page 8 of 38
PIN DESCRIPTION
Pin #
1, 24, 61, 72,
86, 87, 93, 97-
100
2
3, 6, 89, 92
74-77, 83
17, 23, 30, 47,
57, 64
11, 15, 21, 28,
45, 56, 66
4, 5, 73, 78,
79, 82, 85, 88,
96
13, 16,22,
29,46,58,62,63
65
7
Mnemonic
NC
I/O
Description
Not Connected. Allow device pin to float.
PLL_LOOP_FILTER
AVDD (1.8V)
AVDD (3.3V)
DVDD (1.8V)
I
I
I
I
PLL loop filter compensation pin.
Analog Core VDD: 1.8V Analog Supply.
Analog DAC VDD: 3.3V Analog Supply.
Digital Core VDD: 1.8V Digital Supply.
DVDD_I/O (3.3V)
I
Digital Input/Output VDD: 3.3V Digital Supply.
AGND
I
Analog Ground.
DGND
I
Digital Ground.
SYNC_IN+
I
Digital input (rising edge active). Synchronization signal from external master to
synchronize internal sub-clocks.
Digital input (rising edge active). Synchronization signal from external master to
synchronize internal sub-clocks.
Digitaloutput (rising edge active). Synchronization signal from internal device sub-
clocks to synchronize external slave devices.
Digitaloutput (rising edge active). Synchronization signal from internal device sub-
clocks to synchronize external slave devices.
Digital output (active high). Sync sample error: A high on this pin indicates that the
AD9957 did not receive a valid sync signal on SYNC_I+/SYNC_I-.
Digital Input (active high). Master reset: clears all memory elements and sets registers
to default values.
Digital input (active high). External Power Down: A high level on this pin initates the
currently programmed power down mode. Please see the Power Down Modes section
of this document for further details. If unused, tie to ground.
Digital output (active high). PLL_Lock: A high indicates the clock multiplier PLL has
acquired lock to the reference clock input.
Digital output (active high). CCI Overflow: A high indicates a CCI filter overflow. This
pin will remain high until the CCI overflow condition is cleared.
Parallel data input bus (active high). These pins provide the interleaved 18 bit digital I
& Q vectors for the modulator to upconvert.
In Blackfin interface mode, this pin serves as the I-data serial input.
In Blackfin interface mode, this pin serves as the Q-data serial input.
Digital output (clock) Parallel Data Clock see Signal Processing section for details
Digital input (active high). Transmit enable: see Signal Processing section for details
In Blackfin interface mode, this pin serves as the FS Input, to receive the RFS OUTPUT
signal from the ADSP BF533
Digital input (active high). Input Scaling Function Control: Control for the RAM
amplitude scaling function. When this function is engaged, a high sweeps the
amplitude from the beginning RAM address to the end. A low sweeps the amplitude
from the end RAM address to the beginning.
Digital inputs (active high). Profile select pins: used to select one of eight
phase/frequency profiles for the DDS core (single-tone or carrier tone). Changing the
state of one of these pins will transfer the current contents of all I/O buffers to the
corresponding registers. State changes should be setup to the IO_SYNC_CLK pin.
Digital output (clock). Outputs System clock/4. The I/O_UPDATE and PROFILE<2:0>
pins should be setup to the rising edge of this signal.
8
SYNC_IN-
I
9
SYNC_OUT+
O
10
SYNC_OUT-
O
12
SYNC_SMP_ERR
O
14
MASTER _RESET
I
18
EXT_PWR_DWN
I
19
PLL_LOCK
O
20
CCI_OVFL
O
25-27, 31-39,
42-44, 48-50
42
43
40
41
41
D<17:0>
I
SPORT I-DATA
SPORT Q-DATA
PDCLK/TSCLK
TxENABLE
FS
I
I
O
I
I
51
ISFC
I
52-54
PROFILE <2:0>
I
55
SYNC_CLK
O
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