參數(shù)資料
型號(hào)： AD9956YCPZ-REEL7
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 1/32頁(yè)
文件大?。?/td> 0K
描述： IC SYNTHESIZER 1.8V 48LFCSP
產(chǎn)品培訓(xùn)模塊： Direct Digital Synthesis Tutorial Series (1 of 7): Introduction
Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action
Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter
Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction
Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter
Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator
標(biāo)準(zhǔn)包裝： 750
分辨率（位）： 14 b
主 fclk： 3GHz
調(diào)節(jié)字寬（位）： 48 b
電源電壓： 1.71 V ~ 1.96 V
工作溫度： -40°C ~ 125°C
安裝類型： 表面貼裝
封裝/外殼： 48-VFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 48-LFCSP-VQ（7x7）
包裝： 帶卷 (TR)
配用： AD9956-VCO/PCBZ-ND - BOARD EVAL 14BIT 1.8V 48LFCSP
AD9956/PCBZ-ND - BOARD EVAL FOR AD9956
2.7 GHz DDS-Based AgileRFTM Synthesizer
AD9956
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.326.8703
2004 Analog Devices, Inc. All rights reserved.
FEATURES
400 MSPS internal DDS clock speed
48-bit frequency tuning word
14-bit programmable phase offset
Integrated 14-bit DAC
Excellent dynamic performance
Phase noise ≤ 135 dBc/Hz @ 1 KHz offset
80 dB SFDR @ 160 MHz (±100 KHz offset IOUT)
25 Mb/s write-speed serial I/O control
200 MHz phase frequency detector inputs
655 MHz programmable input dividers for the phase
frequency detector (÷M, ÷N) {M, N = 1..16} (bypassable)
Programmable RF divider (÷R) {R = 1, 2, 4, 8} (bypassable)
8 phase/frequency profiles
1.8 V supply for device operation
3.3 V supply for I/O and charge pump
Software controlled power-down
48-lead LFCSP package
Automatic linear frequency sweeping capability (in DDS)
Programmable charge pump current (up to 4 mA)
Phase modulation capability
Multichip synchronization
Dual-mode PLL lock detect
655 MHz CML-mode PECL-compliant driver
APPLICATIONS
Agile LO frequency synthesis
FM chirp source for radar and scanning systems
Automotive radars
Test and measurement equipment
Acousto-optic device drivers
FUNCTIONAL BLOCK DIAGRAM
FREQUENCY
ACCUMULATOR
PHASE
ACCUMULATOR
PHASE
OFFSET
PHASE
OFFSET
WORD
TIMING AND CONTROL LOGIC
PHASE TO
AMPLITUDE
CONVERSION
14
FTW
48
24
DAC
RF-DIVIDER
÷R
FROM PLLOSC
3
PS<2:0> RESET I/O PORT
CHARGE
PUMP
SCALER
Φ
BUFFER
CP_OUT
CP_RSET
PLL_LOCK/SYNC_IN
I/O_UPDATE
SYNC_OUT
REFCLK
CML CLOCK DRIVER
DRV DRV DRV_RSET
DAC_RSET
IOUT
SYNC_CLK
SYSCLK
DELTA
FREQUENCY
TUNING WORD
DELTA
FREQUENCY
RAMP RATE
SYSCLK
3
LOCK
DETECT
48
19
14
DDS CORE
SYSCLK
I/O_RESET
OSCILLATOR
16
CHARGE
PUMP
PLLREF/
PLLREF
PLLOSC/
PLLOSC
÷N
÷4
÷M
04806-0-001
Figure 1.
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