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參數(shù)資料
| 型號(hào)： | AD9901KPZ |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 6/8頁(yè) |
| 文件大小： | 0K |
| 描述： | IC PHS/FREQ DISCRIMINATOR 20PLCC |
| 標(biāo)準(zhǔn)包裝： | 49 |
| 類(lèi)型： | 數(shù)字相位/頻率鑒別器 |
| PLL： | 是 |
| 輸入： | CMOS，ECL，TTL |
| 輸出： | CMOS，ECL，TTL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:1 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 200MHz |
| 電源電壓： | 5V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類(lèi)型： | 表面貼裝 |
| 封裝/外殼： | 20-LCC（J 形引線） |
| 供應(yīng)商設(shè)備封裝： | 20-PLCC（9x9） |
| 包裝： | 管件 |
| 產(chǎn)品目錄頁(yè)面： | 551 (CN2011-ZH PDF) |
AD9901
REV. B
–6–
THEORY OF OPERATION
A phase detector is one of three basic components of a phase-
locked loop (PLL); the other two are a filter and a tunable oscil-
lator. A basic PLL control system is shown in Figure 3.
LOW-
PASS
FILTER
1/N
VCO
AD9901
REFERENCE
INPUT
OSCILLATOR
OUTPUT
OPTIONAL 1/N PRESCALER
TYPICAL OF DIGITAL PLLs
Figure 3. Phase-Locked Loop Control System
The function of the phase detector is to generate an error signal
that is used to retune the oscillator frequency whenever its out-
put deviates from a reference input signal. The two most com-
mon methods of implementing phase detectors are (1) an analog
mixer and (2) a family of sequential logic circuits known as
digital phase detectors.
The AD9901 is a digital phase detector. As illustrated in the
block diagram of the unit, straightforward sequential logic de-
sign is used. The main components include four “D” flip-flops,
an exclusive-OR gate (XOR) and some combinational output
logic. The circuit operates in two distinct modes: as a linear
phase detector and as a frequency discriminator.
When the reference and oscillator are very close in frequency,
only the phase detection circuit is active. If the two inputs are
substantially different in frequency, the frequency discrimina-
tion circuit overrides the phase detector portion to drive the
oscillator frequency toward the reference frequency and put it
within range of the phase detector.
Input signals to the AD9901 are pulse trains, and its output
duty cycle is proportional to the phase difference of the oscilla-
tor and reference inputs. Figures 4, 5 and 6 illustrate, respec-
tively, the input/output relationships at lock; with the
DC MEAN VALUE
REFERENCE
INPUT
OSCILLATOR
INPUT
REFERENCE
FLIP-FLOP
OUTPUT
OSCILLATOR
FLIP-FLOP
OUTPUT
XORGATE
OUTPUT
Figure 4. AD9901 Timing Waveforms at “Lock”
DC MEAN VALUE
REFERENCE
INPUT
OSCILLATOR
INPUT
REFERENCE
FLIP-FLOP
OUTPUT
OSCILLATOR
FLIP-FLOP
OUTPUT
XORGATE
OUTPUT
Figure 5. Timing Waveforms (
φ
OUT Leads φIN)
DC MEAN VALUE
REFERENCE
INPUT
OSCILLATOR
INPUT
REFERENCE
FLIP-FLOP
OUTPUT
OSCILLATOR
FLIP-FLOP
OUTPUT
XORGATE
OUTPUT
Figure 6. Timing Waveforms (
φ
OUT Lags φIN)
oscillator leading the reference frequency; and with the oscillator
lagging. This output pulse train is low-pass filtered to extract the
dc mean value [Kφ (φI – φO)] where Kφ is a proportionality con-
stant (phase gain).
At or near lock (Figures 4, 5 and 6), only the two input flip-
flops and the exclusive-OR gate (the phase detection circuit) are
active. The input flip-flops divide both the reference and oscilla-
tor frequencies by a factor of two. This insures that inputs to the
exclusive-OR are square waves, regardless of the input duty
cycles of the frequencies being compared. This division-by-two
also moves the nonlinear detection range to the ends of the
range rather than near lock, which is the case with conventional
digital phase detectors.
Figure 7 illustrates the constant gain near lock.
PHASE DIFFERENCE AT INPUTS
2
1
0
–2
0
OUTPUT
VOLTAGE
SWING
–
FO = 50MHz
FO = 70MHz
FO = 200MHz
TYPICAL PHASE DETECTOR
GAIN IS 0.2865V/RAD
VOUT = 1.8V
Figure 7. Phase Gain Plot
When the two square waves are combined by the XOR, the
output has a 50% duty cycle if the reference and oscillator in-
puts are exactly 180
° out of phase; under these conditions, the
AD9901 is operating in a locked mode. Any shift in the phase
relationship between these input signals causes a change in the
output duty cycle. Near lock, the frequency discriminator flip-
flops provide constant HIGH levels to gate the XOR output to
the final output.
The duty cycle of the AD9901 is a direct measure of the phase
difference between the two input signals when the unit is near
lock. The transfer function can be stated as [Kφ(φI – φO](V/RAD),
where Kφ is the allowable output voltage range of the AD9901
divided by 2
π.
For a typical output swing of 1.8 V, the transfer function can be
stated as (1.8 V/2
π = 0.285 V/RAD). Figure 7 shows the rela-
tionship of the dc mean value of the AD9901 output as a func-
tion of the phase difference of the two inputs.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9901KPZ | 制造商:Analog Devices 功能描述:IC DISCRIMINATOR ((NW)) |
| AD9901KPZ-REEL | 功能描述:IC DISCRIMINATOR PH/FREQ 20PLCC RoHS:是 類(lèi)別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:Precision Edge® 類(lèi)型:時(shí)鐘/頻率合成器 PLL:無(wú) 輸入:CML，PECL 輸出:CML 電路數(shù):1 比率 - 輸入:輸出:2:1 差分 - 輸入:輸出:是/是 頻率 - 最大:10.7GHz 除法器/乘法器:無(wú)/無(wú) 電源電壓:2.375 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類(lèi)型:表面貼裝 封裝/外殼:16-VFQFN 裸露焊盤(pán)，16-MLF? 供應(yīng)商設(shè)備封裝:16-MLF?（3x3） 包裝:帶卷 (TR) 其它名稱:SY58052UMGTRSY58052UMGTR-ND |
| AD9901KQ | 功能描述:IC PHASE/FREQ DISCRIMR 14-CDIP RoHS:否 類(lèi)別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:2,000 系列:- 類(lèi)型:PLL 時(shí)鐘發(fā)生器 PLL:帶旁路 輸入:LVCMOS，LVPECL 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:2:11 差分 - 輸入:輸出:是/無(wú) 頻率 - 最大:240MHz 除法器/乘法器:是/無(wú) 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類(lèi)型:表面貼裝 封裝/外殼:32-LQFP 供應(yīng)商設(shè)備封裝:32-TQFP（7x7） 包裝:帶卷 (TR) |
| AD9901TE/883 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Ultrahigh Speed Phase/Frequency Discriminator |
| AD9901TQ/883 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Ultrahigh Speed Phase/Frequency Discriminator |
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