參數(shù)資料
型號： AD9891
廠商： Analog Devices, Inc.
英文描述： CCD Signal Processors with Precision Timing⑩ Generator
中文描述： CCD信號處理器，精確定時⑩發(fā)生器
文件頁數(shù)： 6/59頁
文件大小： 599K
代理商： AD9891
REV. A
–6–
AD9891/AD9895
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
AD9891 and AD9895 feature proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
ABSOLUTE MAXIMUM RATINGS
With
Respect
To
Parameter
Min
Max
Unit
AVDD1, AVDD2
TCVDD
HVDD
RGVDD
DVDD
DRVDD
RG Output
H1
–
H4 Output
Digital Outputs
Digital Inputs
SCK, SL, SDATA
VRT, VRB
BYP1
–
BYP3, CCDIN
Junction Temperature
Lead Temperature, 10 sec
AVSS
TCVSS
HVSS
RGVSS
DVSS
DRVSS
RGVSS
HVSS
DVSS
DVSS
DVSS
AVSS
AVSS
–
0.3
–
0.3
–
0.3
–
0.3
–
0.3
–
0.3
–
0.3
–
0.3
–
0.3
–
0.3
–
0.3
–
0.3
–
0.3
+3.9
+3.9
+5.5
+5.5
+3.9
+3.9
RGVDD + 0.3
HVDD + 0.3
DVDD + 0.3
DVDD + 0.3
DVDD + 0.3
AVDD + 0.3
AVDD + 0.3
150
350
V
V
V
V
V
V
V
V
V
V
V
V
V
°
C
°
C
ORDERING GUIDE
Temperature
Range
–
20
°
C to +85
°
C
–
20
°
C to +85
°
C
Package
Description
Package
Option
Model
AD9891KBC
AD9895KBC
CSPBGA
CSPBGA
BC-64
BC-64
PACKAGE THERMAL CHARACTERISTICS
Thermal Resistance
JA
= 61
°
C/W
JC
= 29.7
°
C/W
TIMING SPECIFICATIONS
Parameter
Symbol
Min
Typ
Max
Unit
MASTER CLOCK, CLI (Figure 7)
CLI Clock Period, AD9891
CLI High/Low Pulsewidth, AD9891
CLI Clock Period, AD9895
CLI High/Low Pulsewidth, AD9895
Delay from CLI Rising Edge to Internal Pixel Position 0
AFE CLAMP PULSES
1
(Figure 13)
CLPDM Pulsewidth
CLPOB Pulsewidth
2
AFE SAMPLE LOCATION
1
(Figure 10)
SHP Sample Edge to SHD Sample Edge, AD9891
SHP Sample Edge to SHD Sample Edge, AD9895
t
CONV
50
20
33.3
13
ns
ns
ns
ns
ns
25
t
CONV
16.7
6
t
CLIDLY
4
2
10
20
Pixels
Pixels
t
S1
t
S1
20
13
25
16.7
ns
ns
DATA OUTPUTS (Figure 12)
Output Delay from DCLK Rising Edge
1
Pipeline Delay from SHP/SHD Sampling
t
OD
8
9
ns
Cycles
SERIAL INTERFACE (Figures 52 and 53)
Maximum SCK Frequency
SL to SCK Setup Time
SCK to SL Hold Time
SDATA Valid to SCK Rising Edge Setup
SCK Falling Edge to SDATA Valid Hold
SCK Falling Edge to SDATA Valid Read
f
SCLK
t
LS
t
LH
t
DS
t
DH
t
DV
10
10
10
10
10
10
MHz
ns
ns
ns
ns
ns
NOTES
1
Parameter is programmable.
2
Minimum CLPOB pulsewidth is for functional operation only. Wider typical pulses are recommended to achieve good clamp performance.
(C
= 20 pF, AVDD = DVDD = DRVDD = 3.0 V, f
CLI
= 20 MHz [AD9891] or 30 MHz [AD9895], unless
otherwise noted.)
WARNING!
ESD SENSITIVE DEVICE
相關PDF資料
PDF描述
AD9895 CCD Signal Processors with Precision Timing⑩ Generator
AD9891KBC CCD Signal Processors with Precision Timing⑩ Generator
AD9895KBC CCD Signal Processors with Precision Timing⑩ Generator
AD9911BCPZ 500 MSPS Direct Digital Synthesizer with 10-Bit DAC
AD9911BCPZ-REEL7 500 MSPS Direct Digital Synthesizer with 10-Bit DAC
相關代理商/技術參數(shù)
參數(shù)描述
AD9891KBC 制造商:Rochester Electronics LLC 功能描述:10 BIT 20 MSPS, 5V/3V AFETG - Bulk 制造商:Analog Devices 功能描述:
ad9891kbcz 制造商:Rochester Electronics LLC 功能描述: 制造商:Analog Devices 功能描述:
AD9895 制造商:AD 制造商全稱:Analog Devices 功能描述:CCD Signal Processors with Precision Timing⑩ Generator
AD9895KBC 制造商:Analog Devices 功能描述:AFE Video 1ADC 12-Bit 3V/5V 64-Pin CSP-BGA 制造商:Rochester Electronics LLC 功能描述:12 BIT 30 MHZ AFE & PRGM TIMING GENERATO - Bulk
AD9895KBCRL 制造商:Analog Devices 功能描述:AFE Video 1ADC 12-Bit 3V/5V 64-Pin CSP-BGA T/R
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