- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄375249 > AD9888 (Analog Devices, Inc.) 100/140/170/205 MSPS Analog Flat Panel Interface PDF資料下載
參數(shù)資料
| 型號： | AD9888 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 100/140/170/205 MSPS Analog Flat Panel Interface |
| 中文描述： | 100/140/170/205 MSPS的模擬平板顯示接口 |
| 文件頁數(shù)： | 6/32頁 |
| 文件大?。?/td> | 249K |
| 代理商： | AD9888 |
第1頁第2頁第3頁第4頁第5頁當前第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁
REV. A
AD9888
–6–
PIN FUNCTION DESCRIPTIONS
Pin
Description
Inputs
R
AIN
0
G
AIN
0
B
AIN
0
R
AIN
1
G
AIN
1
B
AIN
1
Channel 0 Analog Input for RED
Channel 0 Analog Input for GREEN
Channel 0 Analog Input for BLUE
Channel 1 Analog Input for RED
Channel 1 Analog Input for GREEN
Channel 1 Analog Input for BLUE
High-impedance inputs that accept the RED, GREEN, and BLUE channel graphics signals, respectively. (The six
channels are identical and can be used for any colors; colors are assigned for convenient reference.)
They accommodate input signals ranging from 0.5 V to 1.0 V full scale. Signals should be ac-coupled to these pins to
support clamp operation.
Channel 0 Horizontal Sync Input
Channel 1 Horizontal Sync Input
These inputs receive a logic signal that establishes the horizontal timing reference and provides the frequency reference
for pixel clock generation.
The logic sense of this pin is controlled by serial register 0Eh Bit 6 (Hsync Polarity). Only the leading edge of Hsync is
used by the PLL. The trailing edge is used for clamp timing only. When HSPOL = 0, the falling edge of Hsync is used.
When HSPOL = 1, the rising edge is active.
The input includes a Schmitt trigger for noise immunity, with a nominal input threshold of 1.5 V.
Channel 0 Vertical Sync Input
Channel 1 Vertical Sync Input
These are the inputs for vertical sync.
Channel 0 Sync-on-Green Input
Channel 1 Sync-on-Green Input
This input is provided to assist with processing signals with embedded sync, typically on the GREEN channel. The pin is
connected to a high-speed comparator with an internally generated, variable threshold level, which is nominally set to
0.15 V above the negative peak of the input signal.
When connected to an ac-coupled graphics signal with embedded sync, it will produce a noninverting digital output on
SOGOUT. (This is usually a composite sync signal, containing both vertical and horizontal sync information.)
When not used, this input should be left unconnected. For more details on this function and how it should be config-
ured, refer to the Sync-on-Green section.
External Clamp Input
This logic input may be used to define the time during which the input signal is clamped to the reference dc level
(ground for RGB or midscale for YUV). It should be exercised when the reference dc level is known to be present
on
the analog input channels, typically during the back porch of the graphics signal. The CLAMP pin is enabled by setting
the external clamp control (register 0Fh, Bit 7) to 1 (default is 0). When disabled, this pin is ignored and the clamp
timing is determined internally by counting a delay and duration from the trailing edge of the HSYNC input. The logic
sense of this pin is controlled by the clamp polarity control (register 0Fh, Bit 6). When not used, this pin must be grounded
and external clamp programmed to 0.
Clock Generator Coast Input (Optional)
This input may be used to cause the pixel clock generator to stop synchronizing with HSYNC and continue producing
a clock at its current frequency and phase. This is useful when processing signals from sources that fail to produce horizontal
sync pulses when in the vertical interval or that include equalization pulses. The Coast signal is usually
not
required for
PC-generated signals.
The logic sense of this pin is controlled by 0FH Bit 3 (Coast Polarity).
When not used, this pin may be grounded and Coast Polarity programmed to 1, or tied HIGH (to V
D
through a 10 k
resistor)
and Coast Polarity programmed to 0. The Coast Polarity register bit defaults to 1 at power-up.
External Clock Input (Optional)
This pin may be used to provide an external clock to the AD9888, in place of the clock internally generated from
HSYNC. It is enabled by programming the External clock register to 1 (15H, Bit 0). When an external clock is used, all
other internal functions operate normally. When unused, this pin should be tied through a 10 k
resistor to GROUND,
and the External Clock register programmed to 0. The clock phase adjustment still operates when an external clock
source is used.
HSYNC0
HSYNC1
VSYNC0
VSYNC1
SOGIN0
SOGIN1
CLAMP
COAST
CKEXT
相關PDF資料 |
PDF描述 |
|---|---|
| AD9888KS-100 | 100/140/170/205 MSPS Analog Flat Panel Interface |
| AD9888KS-140 | TRI N PLUG F 2-13 |
| AD9888KS-170 | TRI N RECP M FLG 2-13 |
| AD9888KS-205 | TRI N RECP M J/N 2-13 |
| AD9891 | CCD Signal Processors with Precision Timing⑩ Generator |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| AD9888/PCB | 制造商:AD 制造商全稱:Analog Devices 功能描述:100/140/170/205 MSPS Analog Flat Panel Interface |
| AD9888_11 | 制造商:AD 制造商全稱:Analog Devices 功能描述:100 MSPS/140 MSPS/170 MSPS Analog Flat Panel Interface |
| AD98888KS | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| AD9888KS-100 | 制造商:Analog Devices 功能描述:ADC Triple 100Msps 8-bit Parallel 128-Pin MQFP 制造商:Rochester Electronics LLC 功能描述:100 MHZ ANALOG GRAPHICS INTERFACE CHIP - Bulk |
| AD9888KS-140 | 制造商:Rochester Electronics LLC 功能描述:140MHZ ANALOG GRAPHICS INTERFACE CHIP - Bulk 制造商:Analog Devices 功能描述: |
發(fā)布緊急采購，3分鐘左右您將得到回復。