- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄11768 > AD9883ABSTZ-RL110 (Analog Devices Inc)IC INTERFACE FLAT 110MHZ 80LQFP PDF資料下載
參數(shù)資料
| 型號： | AD9883ABSTZ-RL110 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 3/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC INTERFACE FLAT 110MHZ 80LQFP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 應(yīng)用： | 顯示器，監(jiān)控器，電視 |
| 接口： | 模擬 |
| 電源電壓： | 3 V ~ 3.6 V |
| 封裝/外殼： | 80-LQFP |
| 供應(yīng)商設(shè)備封裝： | 80-LQFP（14x14） |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 安裝類型： | 表面貼裝 |
| 其它名稱： | AD9883ABSTZ-RL110DKR |
第1頁第2頁當(dāng)前第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁
REV. B
AD9883A
–11–
GAIN
1.0
0.
0
00H
FFH
INPUT
RANGE
–
V
0.5
OFFSET = 00H
OFFSET = 3FH
OFFSET = 7FH
OFFSET = 00H
OFFSET = 7FH
OFFSET = 3FH
Figure 2. Gain and Offset Control
Gain and Offset Control
The AD9883A can accommodate input signals with inputs
ranging from 0.5 V to 1.0 V full scale. The full-scale range is set
in three 8-bit registers (Red Gain, Green Gain, and Blue Gain).
Note that increasing the gain setting results in an image with
less contrast.
The offset control shifts the entire input range, resulting in a
change in image brightness. Three 7-bit registers (Red Offset,
Green Offset, Blue Offset) provide independent settings for
each channel. The offset controls provide a
± 63 LSB adjust-
ment range. This range is connected with the full-scale range, so
if the input range is doubled (from 0.5 V to 1.0 V) then the offset
step size is also doubled (from 2 mV per step to 4 mV per step).
Figure 2 illustrates the interaction of gain and offset controls.
The magnitude of an LSB in offset adjustment is proportional
to the full-scale range, so changing the full-scale range also
changes the offset. The change is minimal if the offset setting is
near midscale. When changing the offset, the full-scale range is
not affected, but the full-scale level is shifted by the same amount
as the zero scale level.
Sync-on-Green
The Sync-on-Green input operates in two steps. First, it sets a
baseline clamp level off of the incoming video signal with a
negative peak detector. Second, it sets the sync trigger level to a
programmable level (typically 150 mV) above the negative peak.
The Sync-on-Green input must be ac-coupled to the Green
analog input through its own capacitor, as shown in Figure 3.
The value of the capacitor must be 1 nF
± 20%. If Sync-on-Green
is not used, this connection is not required. Note that the Sync-
on-Green signal is always negative polarity.
RAIN
BAIN
GAIN
SOG
47nF
1nF
Figure 3. Typical Clamp Configuration
Clock Generation
A phase locked loop (PLL) is employed to generate the pixel
clock. In this PLL, the Hsync input provides a reference fre-
quency. A voltage controlled oscillator (VCO) generates a much
higher pixel clock frequency. This pixel clock is divided by the
PLL divide value (registers 01H and 02H) and phase compared
with the Hsync input. Any error is used to shift the VCO fre-
quency and maintain lock between the two signals.
The stability of this clock is a very important element in provid-
ing the clearest and most stable image. During each pixel time,
there is a period during which the signal is slewing from the old
pixel amplitude and settling at its new value. Then there is a
time when the input voltage is stable, before the signal must
slew to a new value (Figure 4). The ratio of the slewing time to
the stable time is a function of the bandwidth of the graphics
DAC and the bandwidth of the transmission system (cable and
termination). It is also a function of the overall pixel rate. Clearly,
if the dynamic characteristics of the system remain fixed, the
slewing and settling time is likewise fixed. This time must be
subtracted from the total pixel period, leaving the stable period.
At higher pixel frequencies, the total cycle time is shorter, and the
stable pixel time becomes shorter as well.
PIXEL CLOCK
INVALID SAMPLE TIMES
Figure 4. Pixel Sampling Times
Any jitter in the clock reduces the precision with which the
sampling time can be determined, and must also be subtracted
from the stable pixel time.
Considerable care has been taken in the design of the AD9883A’s
clock generation circuit to minimize jitter. As indicated in
Figure 5, the clock jitter of the AD9883A is less than 5% of the
total pixel time in all operating modes, making the reduction in
the valid sampling time due to jitter negligible.
FREQUENCY – MHz
14
12
0
PIXEL
CLOCK
JITTER
(p-p)
–
%
10
8
6
4
2
31.5
36.0 36.0 50.0 56.25
75.0 85.5
110.0
Figure 5. Pixel Clock Jitter vs. Frequency
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| VI-B42-IW-F1 | CONVERTER MOD DC/DC 15V 100W |
| PIC12C509-04I/P | IC MCU OTP 1KX12 8DIP |
| D38999/24WC4PA | CONN RCPT 4POS JAM NUT W/PINS |
| PIC16LF1507-E/P | IC MCU 8BIT 3.5KB FLASH 20PDIP |
| VI-B41-IX-F4 | CONVERTER MOD DC/DC 12V 75W |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9883ABSTZ-RL140 | 功能描述:IC INTERFACE FLAT 140MHZ 80LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 專用 系列:- 標(biāo)準(zhǔn)包裝:3,000 系列:- 應(yīng)用:PDA，便攜式音頻/視頻，智能電話 接口:I²C，2 線串口 電源電壓:1.65 V ~ 3.6 V 封裝/外殼:24-WQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:24-QFN 裸露焊盤（4x4） 包裝:帶卷 (TR) 安裝類型:表面貼裝 產(chǎn)品目錄頁面:1015 (CN2011-ZH PDF) 其它名稱:296-25223-2 |
| AD9883AKST-1 | 制造商:Analog Devices 功能描述: |
| AD9883AKST-110 | 制造商:Analog Devices 功能描述:ADC Triple 110Msps 8-bit Parallel 80-Pin LQFP 制造商:Rochester Electronics LLC 功能描述:110MHZ ANALOG INTERFACE FOR SGA FPD - Bulk 制造商:Analog Devices 功能描述:IC INTERFACE GRAPHIC |
| AD9883AKST-140 | 制造商:Analog Devices 功能描述:ADC Triple 140Msps 8-bit Parallel 80-Pin LQFP 制造商:Analog Devices 功能描述:IC INTERFACE ANALOG |
| AD9883AKSTZ-110 | 功能描述:IC FLAT PANEL INTERFACE 80-LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 專用 系列:- 特色產(chǎn)品:NXP - I2C Interface 標(biāo)準(zhǔn)包裝:1 系列:- 應(yīng)用:2 通道 I²C 多路復(fù)用器 接口:I²C，SM 總線 電源電壓:2.3 V ~ 5.5 V 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:剪切帶 (CT) 安裝類型:表面貼裝 產(chǎn)品目錄頁面:825 (CN2011-ZH PDF) 其它名稱:568-1854-1 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。