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參數(shù)資料
| 型號： | AD9878-EB |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | 模擬前端 |
| 英文描述： | Mixed-Signal Front End for Broadband Applications |
| 中文描述： | 混合信號的寬帶應用前端 |
| 文件頁數(shù)： | 27/36頁 |
| 文件大?。?/td> | 749K |
| 代理商： | AD9878-EB |
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AD9878
∑- OUTPUTS
An on-chip ∑- output provides a digital logic bit stream with
an average duty cycle that varies between 0% and (255/256)%,
depending on the programmed code, as shown in Figure 32.
Rev. A | Page 27 of 36
00h
8 t
MCLK
01h
02h
80h
FFh
256
×
8 t
MCLK
8 t
MCLK
256
×
8 t
MCLK
0
Figure 32. ∑- Output Signals
This bit stream can be low-pass filtered to generate a
programmable dc voltage of
(
DC
Code
V
256
-
)
[
]
L
H
V
V
+
×
∑
=
where:
V
V
V
6
=
=
DRVDD
V
4
H
V
L
In cable set-top box applications, the output can be used to
control external variable gain amplifiers or RF tuners. A
single-pole, RC, low-pass filter provides sufficient filtering
(see Figure 33). In more demanding applications, where
additional gain, level-shift, or drive capability is required,
consider using a first- or second-order filter (see Figure 34).
AD9878
MCLK
DAC
8
CONTROL
WORD
TYPICAL: R = 50k
C = 0.01
μ
F
f
–3dB
= 1/(2
π
RC) = 318Hz
÷
8
Σ
-
R
DC (V
L
TO V
H
)
C
0
Figure 33. ∑- RC Filter
0
AD9878
SIGMA-DELTA
Σ
-
R
C
V
SD
R
V
OUT
R
R1
V
OFFSET
C
OP250
TYPICAL: R = 50k
C = 0.01
μ
F
f
–3dB
= 1/(2
π
RC) = 318Hz
V
OUT
= (V
SD
+ V
OFFSET
) (1 + R/R1)/2
Figure 34. ∑- Active Filter with Gain and Offset
RECEIVE PATH (Rx)
The AD9878 includes three high speed, high performance ADCs.
The 10-bit and dual 12-bit direct-IF ADCs deliver excellent under-
sampling performance with input frequencies as high as 70 MHz.
The sampling rate can be as high as 29 MSPS. The ADC sampling
frequency can be derived directly from the OSCIN signal, or from
the on-chip OSCIN multiplier. For highest dynamic performance,
choose an OSCIN frequency that can be directly used as the
ADC sampling clock. Digital 12-bit ADC outputs are multiplexed
to one 12-bit bus, clocked by a frequency (f
MCLK
) four times the
sampling rate. The IF ADCs use a multiplexer to a 12-bit interface
with an output word rate of f
MCLK
.
IF10 AND IF12 ADC OPERATION
The IF10 and IF12 ADCs have a common architecture and
share several characteristics from an applications standpoint.
Most of the information in the following section is applicable to
both IF ADCs; differences, where they exist, are highlighted.
Input Signal Range and Digital Output Codes
The IF ADCs have differential analog inputs labeled IF+ and IF.
The signal input, V
AIN
, is the voltage difference between the two
input pins, V
AIN
= V
IF+
V
IF
. The full-scale input voltage range is
determined by the internal reference voltages, REFT and REFB,
which define the top and bottom of the scale. The peak input
voltage to the ADC is the difference between REFT and REFB,
which is 1 V p-p. This results in an ADC full-scale input voltage
of 2 V
PPD
. The digital output codes are straight binary and are
shown in Table 11.
Table 11. Digital Output Codes
IF12[11:0]
111…111
111…111
111…110
…
100…001
100…000
011…111
…
000…001
000…000
000…000
Input Signal Voltage
V
AIN
≥ +1.0 V
V
AIN
= +1.0 V 1 LSB
V
AIN
= +1.0 V 2 LSB
…
V
AIN
= 0 V + 1 LSB
V
AIN
= 0.0 V
V
AIN
= 0 V 1 LSB
…
V
AIN
= 1.0 V + 2 LSB
V
AIN
= 1.0 V
V
AIN
< 1.0 V
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| AD9879 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Mixed-Signal Front End Set-Top Box, Cable Modem |
| AD9879_05 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Mixed-Signal Front End Set-Top Box, Cable Modem |
| AD9879BS | 制造商:Analog Devices 功能描述: |
| AD9879BSZ | 功能描述:IC PROCESSOR FRONT END 100MQFP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模擬前端 (AFE) 系列:- 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,500 系列:- 位數(shù):- 通道數(shù):2 功率（瓦特）:- 電壓 - 電源，模擬:3 V ~ 3.6 V 電壓 - 電源，數(shù)字:3 V ~ 3.6 V 封裝/外殼:32-VFQFN 裸露焊盤 供應商設備封裝:32-QFN（5x5） 包裝:帶卷 (TR) |
| AD9879BSZKL1 | 制造商:Rochester Electronics LLC 功能描述: 制造商:Analog Devices 功能描述: |
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