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參數(shù)資料
| 型號： | AD9857AST |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | CMOS 200 MSPS 14-Bit Quadrature Digital Upconverter |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PQFP80 |
| 封裝： | MS-026-BEC, LQFP-80 |
| 文件頁數(shù)： | 3/31頁 |
| 文件大?。?/td> | 551K |
| 代理商： | AD9857AST |
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–3–
AD9857
REV. 0
Test
Level
AD9857
Min
Parameter
Temp
Typ
Max
Unit
SPURIOUS POWER (Off Channel, Measured in
Equivalent Bandwidth), Output Attenuated 18 dB
Relative to Full Scale
6.4 MHz Bandwidth
3.2 MHz Bandwidth
1.6 MHz Bandwidth
0.8 MHz Bandwidth
0.4 MHz Bandwidth
0.2 MHz Bandwidth
25
°
C
25
°
C
25
°
C
25
°
C
25
°
C
25
°
C
IV
IV
IV
IV
IV
IV
–51
–54
–56
–59
–62
–63
dBc
dBc
dBc
dBc
dBc
dBc
TIMING CHARACTERISTICS
Serial Control Bus
Maximum Frequency
Minimum Clock Pulsewidth Low (t
PWL
)
Minimum Clock Pulsewidth High (t
PWH
)
Maximum Clock Rise/Fall Time
Minimum Data Setup Time (t
DS
)
Minimum Data Hold Time (t
DH
)
Maximum Data Valid Time (t
DV
)
Wake-Up Time
1
Minimum RESET Pulsewidth High (t
RH
)
Minimum
CS
Setup Time
25
°
C
25
°
C
25
°
C
25
°
C
25
°
C
25
°
C
25
°
C
25
°
C
25
°
C
25
°
C
I
I
I
I
I
I
I
I
I
I
10
MHz
ns
ns
ms
ns
ns
ns
ms
SYSCLK
2
Cycles
ns
30
30
1
30
0
35
1
5
40
CMOS LOGIC INPUTS
Logic “1” Voltage
Logic “0” Voltage
Logic “1” Current
Logic “0” Current
Input Capacitance
25
°
C
25
°
C
25
°
C
25
°
C
25
°
C
I
I
I
I
V
2.0
V
V
μ
A
μ
A
pF
0.8
5
5
3
CMOS LOGIC OUTPUTS (1 mA LOAD)
Logic “1” Voltage
Logic “0” Voltage
POWER SUPPLY V
S
CURRENT
3
(All Power Specs
at V
DD
= 3.3 V, 25
°
C, REFCLK = 200 MHz)
Full Operating Conditions
160 MHz Clock (
×
16)
120 MHz Clock (
×
12)
Burst Operation (25%)
Single-Tone Mode
Power-Down Mode
Full-Sleep Mode
25
°
C
25
°
C
I
I
2.7
mA
mA
0.4
25
°
C
25
°
C
25
°
C
25
°
C
25
°
C
25
°
C
25
°
C
I
I
I
I
I
I
I
615
515
400
450
310
80
13.5
mA
mA
mA
mA
mA
mA
mA
NOTES
1
Wake-Up Time refers to recovery from Full Sleep Mode. The longest time required is for the Reference Clock Multiplier PLL to lock up (if it is being used). The
Wake-Up Time assumes that there is no capacitor on DAC_BP, and that the recommended PLL loop filter values are used. The state of the Reference Clock Multi-
plier lock can be determined by observing the signal on the PLL_LOCK pin.
2
SYSCLK refers to the actual clock frequency used on-chip by the AD9857. If the Reference Clock Multiplier is used to multiply the external reference frequency, the
SYSCLK frequency is the external frequency multiplied by the Reference Clock Multiplier multiplication factor. If the Reference Clock Multiplier is not
used, the SYSCLK frequency is the same as the external REFCLK frequency.
3
CIC = 2, INV SINC ON, FTW = 40%, PLL OFF, Auto Power-Down Between Burst On, TxENABLE Duty Cycle = 25%.
Specifications subject to change without notice.
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| AD9857ASTZ | 功能描述:IC QUADRATURE DGTL UPCONV 80LQFP RoHS:是 類別:RF/IF 和 RFID >> RF 其它 IC 和模塊 系列:AD9857 標(biāo)準(zhǔn)包裝:100 系列:* |
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| AD9857ASTZ1 | 制造商:AD 制造商全稱:Analog Devices 功能描述:CMOS 200 MSPS 14-Bit Quadrature Digital Upconverter |
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