參數(shù)資料
型號(hào): AD9851BRS
廠商: ANALOG DEVICES INC
元件分類: 模擬信號(hào)調(diào)理
英文描述: CMOS 180 MHz DDS/DAC Synthesizer
中文描述: SPECIALTY ANALOG CIRCUIT, PDSO28
封裝: ULTRA SMALL, MO-150AH, SSOP-28
文件頁數(shù): 5/23頁
文件大?。?/td> 254K
代理商: AD9851BRS
AD9851
–5–
REV. C
PIN FUNCTION DESCRIPTIONS
Pin
No.
Mnemonic
Function
4–1,
28–25
5
6
7
D0–D7
8-Bit Data Input. The data port for loading the 32-bit frequency and 8-bit phase/control words. D7 = MSB;
D0 = LSB. D7, Pin 25, also serves as the input pin for 40-bit serial data word.
6
×
REFCLK Multiplier Ground Connection.
6
×
REFCLK Multiplier Positive Supply Voltage Pin.
Word Load Clock. Rising edge loads the parallel or serial frequency/phase/control words asynchronously
into the 40-bit input register.
Frequency Update. A rising edge asynchronously transfers the contents of the 40-bit input register to be
acted upon by the DDS core. FQ_UD should be issued when the contents of the input register are known
to contain only valid, allowable data.
Reference Clock Input. CMOS/TTL-level pulse train, direct or via the 6
×
REFCLK Multiplier. In direct
mode, this is also the SYSTEM CLOCK. If the 6
×
REFCLK Multiplier is engaged, then the output of the
multiplier is the SYSTEM CLOCK. The rising edge of the SYSTEM CLOCK initiates operations.
Analog Ground. The ground return for the analog circuitry (DAC and Comparator).
Positive supply voltage for analog circuitry (DAC and Comparator, Pin 18) and bandgap voltage reference,
Pin 11.
The DAC’s external R
SET
connection—nominally a 3.92 k
resistor to ground for 10 mA out. This sets
the DAC full-scale output current available from IOUT and IOUTB. R
SET
= 39.93/IOUT
Voltage Output Negative. The comparator’s “complementary” CMOS logic level output.
Voltage Output Positive. The comparator’s “true” CMOS logic level output.
Voltage Input Negative. The comparator’s inverting input.
Voltage Input Positive. The comparator’s noninverting input.
DAC Bypass Connection. This is the DAC voltage reference bypass connection normally NC (NO
CONNECT) for optimum SFDR performance.
The “complementary” DAC output with same characteristics as IOUT except that
IOUTB = (full-scale
output–IOUT)
. Output load should equal that of IOUT for best SFDR performance.
The “true” output of the balanced DAC. Current is “sourcing” and requires current-to-voltage
conversion, usually a resistor or transformer referenced to GND.
IOUT = (full-scale output–IOUTB)
Master Reset pin; active high; clears DDS accumulator and phase offset register to achieve 0 Hz and 0
°
output phase. Sets programming to parallel mode and disengages the 6
×
REFCLK Multiplier. Reset does
not clear the 40-bit input register. On power-up, asserting RESET should be the first priority before pro-
gramming commences.
Positive supply voltage pin for digital circuitry.
Digital Ground. The ground return pin for the digital circuitry.
PGND
PVCC
W_CLK
8
FQ_UD
9
REFCLOCK
10, 19
11, 18
AGND
AVDD
12
R
SET
13
14
15
16
17
VOUTN
VOUTP
VINN
VINP
DACBP
20
IOUTB
21
IOUT
22
RESET
23
24
DVDD
DGND
PIN CONFIGURATION
TOP VIEW
(Not to Scale)
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
AD9851
VOUTP
VOUTN
R
SET
AVDD
AGND
REFCLOCK
FQ UD
D3
D2
D1
LSB D0
PVCC
PGND
VINN
VINP
DACBP
AVDD
AGND
IOUTB
IOUT
D4
D5
D6
D7 MSB/SERIAL LOAD
RESET
DVDD
DGND
W CLK
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參數(shù)描述
AD9851BRSRL 功能描述:IC DDS/DAC SYNTHESIZER 28-SSOP RoHS:否 類別:集成電路 (IC) >> 接口 - 直接數(shù)字合成 (DDS) 系列:- 產(chǎn)品變化通告:Product Discontinuance 27/Oct/2011 標(biāo)準(zhǔn)包裝:2,500 系列:- 分辨率(位):10 b 主 fclk:25MHz 調(diào)節(jié)字寬(位):32 b 電源電壓:2.97 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP(0.173",4.40mm 寬) 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR)
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