參數(shù)資料
型號(hào)： AD9834CRUZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 20/32頁(yè)
文件大小： 0K
描述： IC DDS 10BIT 75MHZ LP 20-TSSOP
產(chǎn)品培訓(xùn)模塊： Direct Digital Synthesis Tutorial Series (1 of 7): Introduction
Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action
Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter
Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction
Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter
Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator
設(shè)計(jì)資源： Amplitude Control Circuit for AD9834 Waveform Generator (CN0156)
標(biāo)準(zhǔn)包裝： 75
分辨率（位）： 10 b
主 fclk： 75MHz
調(diào)節(jié)字寬（位）： 28 b
電源電壓： 2.3 V ~ 5.5 V
工作溫度： -40°C ~ 105°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 20-TSSOP（0.173"，4.40mm 寬）
供應(yīng)商設(shè)備封裝： 20-TSSOP
包裝： 管件
產(chǎn)品目錄頁(yè)面： 552 (CN2011-ZH PDF)
Data Sheet
AD9834
Rev. D | Page 27 of 32
INTERFACING TO MICROPROCESSORS
The AD9834 has a standard serial interface that allows the part
to interface directly with several microprocessors. The device
uses an external serial clock to write the data/control information
into the device. The serial clock can have a frequency of 40 MHz
maximum. The serial clock can be continuous, or it can idle high
or low between write operations. When data/control information is
being written to the AD9834, FSYNC is taken low and is held
low until the 16 bits of data are written into the AD9834. The
FSYNC signal frames the 16 bits of information being loaded
into the AD9834.
AD9834 TO ADSP-21xx INTERFACE
Figure 35 shows the serial interface between the AD9834 and
the ADSP-21xx. The ADSP-21xx should be set up to operate in
the SPORT transmit alternate framing mode (TFSW = 1). The
ADSP-21xx is programmed through the SPORT control register
and should be configured as follows:
Internal clock operation (ISCLK = 1)
Active low framing (INVTFS = 1)
16-bit word length (SLEN = 15)
Internal frame sync signal (ITFS = 1)
Generate a frame sync for each write (TFSR = 1)
Transmission is initiated by writing a word to the Tx register
after the SPORT has been enabled. The data is clocked out on
each rising edge of the serial clock and clocked into the AD9834
on the SCLK falling edge.
1ADDITIONAL PINS OMITTED FOR CLARITY.
AD98341
FSYNC
SDATA
SCLK
TFS
DT
SCLK
ADSP-21xx1
0
270
5-
0
32
AD9834 TO 68HC11/68L11 INTERFACE
Figure 36 shows the serial interface between the AD9834 and
the 68HC11/68L11 microcontroller. The microcontroller is
configured as the master by setting Bit MSTR in the SPCR to 1,
providing a serial clock on SCK while the MOSI output drives
the serial data line SDATA. Because the microcontroller does
not have a dedicated frame sync pin, the FSYNC signal is derived
from a port line (PC7). The setup conditions for correct
operation of the interface are as follows:
SCK idles high between write operations (CPOL = 0)
Data is valid on the SCK falling edge (CPHA = 1)
When data is being transmitted to the AD9834, the FSYNC line is
taken low (PC7). Serial data from the 68HC11/68L11 is transmitted
in 8-bit bytes with only eight falling clock edges occurring in the
transmit cycle. Data is transmitted MSB first. To load data into
the AD9834, PC7 is held low after the first eight bits are transferred
and a second serial write operation is performed to the AD9834.
Only after the second eight bits have been transferred should
FSYNC be taken high again.
1ADDITIONAL PINS OMITTED FOR CLARITY.
AD98341
FSYNC
SDATA
SCLK
68HC11/68L111
PC7
MOSI
SCK
02
70
5-
03
3
Figure 36. 68HC11/68L11 to AD9834 Interface
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