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參數(shù)資料
| 型號(hào)： | AD9831AST |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 數(shù)字信號(hào)處理外設(shè) |
| 英文描述： | CMOS Complete DDS |
| 中文描述： | 16-BIT, DSP-NUM CONTROLLED OSCILLATOR, PQFP48 |
| 封裝： | TQFP-48 |
| 文件頁數(shù)： | 6/16頁 |
| 文件大?。?/td> | 172K |
| 代理商： | AD9831AST |
AD9831
–6–
REV. A
±
2 MHz about the fundamental frequency. T he narrow band
SFDR gives the attenuation of the largest spur or harmonic in a
bandwidth of
±
50 kHz about the fundamental frequency.
Clock Feedthrough
T here will be feedthrough from the MCLK input to the analog
output. Clock feedthrough refers to the magnitude of the
MCLK signal relative to the fundamental frequency in the
AD9831’s output spectrum.
T able I. Control Registers
Register
Size
Description
FREQ0 REG
32 Bits
Frequency Register 0. T his de-
fines the output frequency, when
FSELECT = 0, as a fraction of the
MCLK frequency.
Frequency Register 1. T his de-
fines the output frequency, when
FSELECT = 1, as a fraction of the
MCLK frequency.
Phase Offset Register 0. When
PSEL0 = PSEL1 = 0, the contents
of this register are added to the
output of the phase accumulator.
Phase Offset Register 1. When
PSEL0 = 1 and PSEL1 = 0, the con-
tents of this register are added to
the output of the phase accumulator.
Phase Offset Register 2. When
PSEL0 = 0 and PSEL1 = 1, the con-
tents of this register are added to
the output of the phase accumulator.
Phase Offset Register 3. When
PSEL0 = PSEL1 = 1, the contents
of this register are added to the
output of the phase accumulator.
FREQ1 REG
32 Bits
PHASE0 REG
12 Bits
PHASE1 REG
12 Bits
PHASE2 REG
12 Bits
PHASE3 REG
12 Bits
T able II. Addressing the Control Registers
A2
A1
A0
Destination Register
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
FREQ0 REG 16 LSBs
FREQ0 REG 16 MSBs
FREQ1 REG 16 LSBs
FREQ1 REG 16 MSBs
PHASE0 REG
PHASE1 REG
PHASE2 REG
PHASE3 REG
T E RMINOLOGY
Integral Nonlinearity
T his is the maximum deviation of any code from a straight line
passing through the endpoints of the transfer function. T he
endpoints of the transfer function are zero scale, a point 0.5
LSB below the first code transition (000 . . . 00 to 000 . . . 01)
and full scale, a point 0.5 LSB above the last code transition
(111 . . . 10 to 111 . . . 11). T he error is expressed in LSBs.
Differential Nonlinearity
T his is the difference between the measured and ideal 1 LSB
change between two adjacent codes in the DAC.
Signal to (Noise + Distortion)
Signal to (Noise + Distortion) is measured signal to noise at the
output of the DAC. T he signal is the rms magnitude of the
fundamental. Noise is the rms sum of all the nonfundamental
signals up to half the sampling frequency (f
MCLK
/2) but exclud-
ing the dc component. Signal to (Noise + Distortion) is
dependent on the number of quantization levels used in the
digitization process; the more levels, the smaller the quantiza-
tion noise. T he theoretical Signal to (Noise + Distortion) ratio
for a sine wave input is given by
Signal to
(
Noise
+
Distortion
) = (6.02
N
+ 1.76) dB
where
N
is the number of bits. T hus, for an ideal 10-bit con-
verter, Signal to (Noise + Distortion) = 61.96 dB.
T otal Harmonic Distortion
T otal Harmonic Distortion (T HD) is the ratio of the rms sum
of harmonics to the rms value of the fundamental. For the
AD9831, T HD is defined as
THD
=
20log
(
V
2
2
+
V
3
2
+
V
4
V
1
2
+
V
5
2
+
V
6
2
where
V
1
is the rms amplitude of the fundamental and
V
2
,
V
3
,
V
4
,
V
5
and
V
6
are the rms amplitudes of the second through the
sixth harmonic.
Output Compliance
T he output compliance refers to the maximum voltage which
can be generated at the output of the DAC to meet the specifi-
cations. When voltages greater than that specified for the
output compliance are generated, the AD9831 may not meet
the specifications listed in the data sheet.
Spurious Free Dynamic Range
Along with the frequency of interest, harmonics of the funda-
mental frequency and images of the MCLK frequency are
present at the output of a DDS device. T he spurious free dy-
namic range (SFDR) refers to the largest spur or harmonic
which is present in the band of interest. T he wide band SFDR
gives the magnitude of the largest harmonic or spur relative to
the magnitude of the fundamental frequency in the bandwidth
T able III. Frequency Register Bits
D15
D 0
MSB
L SB
T able IV. Phase Register Bits
D15
D14
D13
D12
D11
D 0
X
X
X
X
MSB
L SB
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PDF描述 |
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| AD9832 | CMOS Complete DDS |
| AD9832BRU | CMOS Complete DDS |
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| AD9833BRM | +2.5 V to +5.5 V, 25 MHz Low Power CMOS Complete DDS |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9831AST-REEL | 制造商:Analog Devices 功能描述:Direct Digital Synthesizer 25MHz 1-DAC 10-Bit Parallel 48-Pin LQFP T/R 制造商:Rochester Electronics LLC 功能描述:25 MHZ +5V/+3V, 10-BIT DDS DAC I.C. - Tape and Reel |
| AD9831ASTZ | 功能描述:IC DDS 10BIT 25MHZ CMOS 48-LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 直接數(shù)字合成 (DDS) 系列:- 產(chǎn)品變化通告:Product Discontinuance 27/Oct/2011 標(biāo)準(zhǔn)包裝:2,500 系列:- 分辨率（位）:10 b 主 fclk:25MHz 調(diào)節(jié)字寬（位）:32 b 電源電壓:2.97 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR) |
| AD9831ASTZKL1 | 制造商:Rochester Electronics LLC 功能描述: 制造商:Analog Devices 功能描述: |
| AD9831ASTZ-REEL | 功能描述:IC DDS 10BIT 25MHZ CMOS 48TQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 直接數(shù)字合成 (DDS) 系列:- 產(chǎn)品變化通告:Product Discontinuance 27/Oct/2011 標(biāo)準(zhǔn)包裝:2,500 系列:- 分辨率（位）:10 b 主 fclk:25MHz 調(diào)節(jié)字寬（位）:32 b 電源電壓:2.97 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR) |
| AD9832 | 制造商:AD 制造商全稱:Analog Devices 功能描述:CMOS Complete DDS |
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