參數(shù)資料
型號: AD9830AST
廠商: ANALOG DEVICES INC
元件分類: 數(shù)字信號處理外設(shè)
英文描述: CMOS Complete DDS
中文描述: 16-BIT, DSP-NUM CONTROLLED OSCILLATOR, PQFP48
封裝: TQFP-48
文件頁數(shù): 9/16頁
文件大?。?/td> 218K
代理商: AD9830AST
AD9830
REV. A
–9–
RBW 1kHz VBW 3kHz ST 50 SEC
1
0
–10
–90
START 0Hz
STOP 25MHz
–40
–60
–70
–80
–20
–30
–50
Figure 17. f
MCLK
= 50 MHz, f
OUT
= 16.5 MHz, Frequency
Word = 547AE148
Register
Size
Description
FREQ0 REG
32 Bits
Frequency Register 0. T his defines
the output frequency, when
FSELECT = 0, as a fraction of the
MCLK frequency.
Frequency Register 1. T his de-
fines the output frequency, when
FSELECT = 1, as a fraction of the
MCLK frequency.
Phase Offset Register 0. When
PSEL0 = PSEL1 = 0, the contents
of this register are added to the out-
put of the phase accumulator.
Phase Offset Register 1. When
PSEL0 = 1 and PSEL1 = 0, the
contents of this register are added
to the output of the phase
accumulator.
Phase Offset Register 2. When
PSEL0 = 0 and PSEL1 = 1, the
contents of this register are added
to the output of the phase
accumulator.
Phase Offset Register 3. When
PSEL0 = PSEL1 = 1, the contents
of this register are added to the out-
put of the phase accumulator.
FREQ1 REG
32 Bits
PHASE0 REG
12 Bits
PHASE1 REG
12 Bits
PHASE2 REG
12 Bits
PHASE3 REG
12 Bits
Figure 18. AD9830 Control Registers
A2
A1
A0
Destination Register
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
FREQ0 REG 16 LSBs
FREQ0 REG 16 MSBs
FREQ1 REG 16 LSBs
FREQ1 REG 16 MSBs
PHASE0 REG
PHASE1 REG
PHASE2 REG
PHASE3 REG
Figure 19. Addressing the Control Registers
D15
D0
MSB
LSB
Figure 20. Frequency Register Bits
D15
D14 D13 D12 D11
D0
X
X
X
X
MSB
LSB
X = Don't Care
Figure 21. Phase Register Bits
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