- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄373968 > AD9830 (Analog Devices, Inc.) CMOS Complete DDS PDF資料下載
參數(shù)資料
| 型號(hào)： | AD9830 |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | XO, clock |
| 英文描述： | CMOS Complete DDS |
| 中文描述： | 完整的DDS的CMOS |
| 文件頁數(shù)： | 5/16頁 |
| 文件大?。?/td> | 218K |
| 代理商： | AD9830 |
AD9830
REV. A
–5–
PIN DE SCRIPT ION
Mnemonic
Function
POWE R SUPPLY
AVDD
Positive power supply for the analog section. A 0.1
μ
F capacitor should be connected between AVDD and
AGND. AVDD has a value of +5 V
±
5%.
Analog Ground.
Positive power supply for the digital section. A 0.1
μ
F decoupling capacitor should be connected between DVDD
and DGND. DVDD has a value of +5 V
±
5%.
Digital Ground.
AGND
DVDD
DGND
ANALOG SIGNAL AND RE FE RE NCE
IOUT ,
IOUT
Current Output. T his is a high impedance current source. A load resistor should be connected between IOUT
and AGND.
IOUT
should be either tied directly to AGND or through an external load resistor to AGND.
FS ADJUST
Full-Scale Adjust Control. A resistor (R
SET
) is connected between this pin and AGND. T his determines the mag-
nitude of the full-scale DAC current. T he relationship between R
SET
and the full-scale current is as follows:
IOUT
FULL-SCALE
= 16
V
REFIN
/R
SET
V
REFIN
= 1.21
V nominal
,
R
SET
= 1 k
typical
REFIN
Voltage Reference Input. T he AD9830 can be used with either the on-board reference, which is available from pin
REFOUT , or an external reference. T he reference to be used is connected to the REFIN pin. T he AD9830 ac-
cepts a reference of 1.21 V nominal.
REFOUT
Voltage Reference Output. T he AD9830 has an on-board reference of value 1.21 V nominal. T he reference is
made available on the REFOUT pin. T his reference is used as the reference to the DAC by connecting REFOUT
to REFIN. REFOUT should be decoupled with a 10 nF capacitor to AGND.
COMP
Compensation pin. T his is a compensation pin for the internal reference amplifier. A 10 nF decoupling ceramic
capacitor should be connected between COMP and AVDD.
DIGIT AL INT E RFACE AND CONT ROL
MCLK
Digital Clock Input. DDS output frequencies are expressed as a binary fraction of the frequency of MCLK . T he
output frequency accuracy and phase noise are determined by this clock.
FSELECT
Frequency Select Input. FSELECT controls which frequency register, FREQ0 or FREQ1, is used in the phase ac-
cumulator. FSELECT is sampled on the rising MCLK edge. FSELECT needs to be in steady state when an
MCLK rising edge occurs. If FSELECT changes value when an MCLK rising edge occurs, there is an uncertainty
of one MCLK cycle as to when control is transferred to the other frequency register. T o avoid any uncertainty, a
change on FSELECT should not coincide with an MCLK rising edge.
WR
Write, Edge-T riggered Digital Input. T he
WR
pin is used when writing data to the AD9830. T he data is loaded
into the AD9830 on the rising edge of the
WR
pulse. T his data is then loaded into the destination register on the
MCLK rising edge. T he
WR
pulse rising edge should not coincide with the MCLK rising edge as there will be an
uncertainty of one MCLK cycle regarding the loading of the destination register with the new data. T he
WR
ris-
ing edge should occur before an MCLK rising edge. T he data will then be transferred into the destination register
on the MCLK rising edge. Alternatively, the
WR
rising edge can occur after the MCLK rising edge and the desti-
nation register will be loaded on the next MCLK rising edge.
D0–D15
Data Bus, Digital Inputs for destination registers.
A0–A2
Address Digital Inputs. T hese address bits are used to select the destination register to which the digital data is to
be written.
PSEL0, PSEL1
Phase Select Input. T he AD9830 has four phase registers. T hese registers can be used to alter the value being in-
put to the SIN ROM. T he contents of the phase register can be added to the phase accumulator output, the inputs
PSEL0 and PSEL1 selecting the phase register to be used. Like the FSELECT input, the AD9830 samples the
PSEL0 and PSEL1 inputs on the MCLK rising edge. T herefore, these inputs should be in steady state at the
MCLK rising edge or, there is an uncertainty of one MCLK cycle as to when control is transferred to the selected
phase register.
SLEEP
Low Power Control, active low digital input.
SLEEP
puts the AD9830 into a low power mode. Internal clocks
are disabled and the DAC’s current sources and REFOUT are turned off. T he AD9830 is re-enabled by taking
SLEEP
high.
RESET
Reset, active low digital input.
RESET
resets the phase accumulator to zero which corresponds to an analog
output of midscale.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD9830AST | CMOS Complete DDS |
| AD9831 | CMOS Complete DDS |
| AD9831AST | CMOS Complete DDS |
| AD9832 | CMOS Complete DDS |
| AD9832BRU | CMOS Complete DDS |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9830AST | 制造商:Analog Devices 功能描述:Direct Digital Synthesizer 50MHz 1-DAC 10-Bit Parallel 48-Pin LQFP 制造商:Rochester Electronics LLC 功能描述:50 MHZ 10-BIT DDS DAC I.C. - Tape and Reel 制造商:Analog Devices 功能描述:IC 10BIT DAC DDS 50 MHZ SMD 9830 |
| AD9830AST-REEL | 制造商:Analog Devices 功能描述:Direct Digital Synthesizer 50MHz 1-DAC 10-Bit Parallel 48-Pin LQFP T/R 制造商:Rochester Electronics LLC 功能描述:50 MHZ 10-BIT DDS DAC I.C. - Tape and Reel |
| AD9830ASTZ | 功能描述:IC DDS 10BIT 50MHZ CMOS 48-TQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 直接數(shù)字合成 (DDS) 系列:- 產(chǎn)品變化通告:Product Discontinuance 27/Oct/2011 標(biāo)準(zhǔn)包裝:2,500 系列:- 分辨率（位）:10 b 主 fclk:25MHz 調(diào)節(jié)字寬（位）:32 b 電源電壓:2.97 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR) |
| AD9830ASTZ-REEL | 功能描述:IC DDS 10BIT 50MHZ CMOS 48TQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 直接數(shù)字合成 (DDS) 系列:- 產(chǎn)品變化通告:Product Discontinuance 27/Oct/2011 標(biāo)準(zhǔn)包裝:2,500 系列:- 分辨率（位）:10 b 主 fclk:25MHz 調(diào)節(jié)字寬（位）:32 b 電源電壓:2.97 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR) |
| AD9831 | 制造商:AD 制造商全稱:Analog Devices 功能描述:CMOS Complete DDS |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。