參數(shù)資料
型號(hào): AD9822
廠商: Analog Devices, Inc.
英文描述: Complete 14-Bit CCD/CIS Signal Processor
中文描述: 完整的14位防治荒漠化公約/ CIS信號(hào)處理器
文件頁(yè)數(shù): 4/15頁(yè)
文件大?。?/td> 150K
代理商: AD9822
REV. A
AD9822
–4–
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD9822 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
ABSOLUTE MAXIMUM RATINGS
*
With
Respect
To
Parameter
Min
Max
Unit
VIN, CAPT, CAPB
Digital Inputs
AVDD
DRVDD
AVSS
Digital Outputs
Junction Temperature
Storage Temperature
Lead Temperature
(10 sec)
AVSS
AVSS
AVSS
DRVSS
DRVSS
DRVSS
–0.3
–0.3
–0.5
–0.5
–0.3
–0.3
AVDD + 0.3
AVDD + 0.3
+6.5
+6.5
+0.3
DRVDD + 0.3
150
+150
V
V
V
V
V
V
°
C
°
C
–65
300
°
C
*
Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum ratings
for extended periods may affect device reliability.
ORDERING GUIDE
Temperature
Range
0
°
C to 70
°
C
0
°
C to 70
°
C
Package
Description
Model
AD9822JR
AD9822JRS
28-Lead 300 Mil SOIC
28-Lead 5.3 mm SSOP
THERMAL CHARACTERISTICS
Thermal Resistance
28-Lead 300 Mil SOIC
θ
JA
= 71.4
°
C/W
θ
JC
= 23
°
C/W
28-Lead 5.3 mm SSOP
θ
JA
= 109
°
C/W
θ
JC
= 39
°
C/W
PIN CONFIGURATION
TOP VIEW
(Not to Scale)
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
AD9822
CDSCLK1
AVDD
CDSCLK2
AVSS
ADCCLK
VINR
OEB
OFFSET
DRVDD
VING
DRVSS
CML
(MSB) D7
VINB
D6
CAPT
D5
CAPB
D4
AVSS
D3
AVDD
D2
SLOAD
D1
SCLK
(LSB) D0
SDATA
PIN FUNCTION DESCRIPTIONS
Pin
N
o.
Name
Type
Description
1
CDSCLK1
DI
CDS Reference Level Sampling
Clock
CDS Data Level Sampling Clock
A/D Converter Sampling Clock
Output Enable, Active Low
Digital Output Driver Supply
Digital Output Driver Ground
Data Output MSB. ADC DB13
High Byte, ADC DB5 Low Byte
Data Output. ADC DB12 High
Byte, ADC DB4 Low Byte
Data Output. ADC DB11 High
Byte, ADC DB3 Low Byte
Data Output. ADC DB10 High
Byte, ADC DB2 Low Byte
Data Output. ADC DB9 High
Byte, ADC DB1 Low Byte
Data Output. ADC DB8 High
Byte, ADC DB0 Low Byte
Data Output. ADC DB7 High
Byte, Don’t Care Low Byte
Data Output LSB. ADC DB6
High Byte, Don’t Care Low Byte
Serial Interface Data Input/Output
Serial Interface Clock Input
Serial Interface Load Pulse
5 V Analog Supply
Analog Ground
ADC Bottom Reference Voltage
Decoupling
ADC Top Reference Voltage
Decoupling
Analog Input, Blue Channel
Internal Bias Level Decoupling
Analog Input, Green Channel
Clamp Bias Level Decoupling
Analog Input, Red Channel
Analog Ground
5 V Analog Supply
2
3
4
5
6
7
CDSCLK2
ADCCLK
OEB
DRVDD
DRVSS
D7
DI
DI
DI
P
P
DO
8
D6
DO
9
D5
DO
10
D4
DO
11
D3
DO
12
D2
DO
13
D1
DO
14
D0
DO
15
16
17
18
19
20
SDATA
SCLK
SLOAD
AVDD
AVSS
CAPB
DI/DO
DI
DI
P
P
AO
21
CAPT
AO
22
23
24
25
26
27
28
VINB
CML
VING
OFFSET
VINR
AVSS
AVDD
AI
AO
AI
AO
AI
P
P
TYPE: AI = Analog Input, AO = Analog Output, DI = Digital Input, DO =
Digital Output, P = Power.
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