- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄373968 > AD9821KST (ANALOG DEVICES INC) Complete 12-Bit 40 MSPS Imaging Signal Processor PDF資料下載
參數(shù)資料
| 型號： | AD9821KST |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | Complete 12-Bit 40 MSPS Imaging Signal Processor |
| 中文描述： | 1-CH 12-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP48 |
| 封裝： | 1.40 MM, PLASTIC, MS-026BBC, LQFP-48 |
| 文件頁數(shù)： | 6/16頁 |
| 文件大?。?/td> | 277K |
| 代理商： | AD9821KST |
REV. 0
–6–
AD9821
DEFINITIONS OF SPECIFICATIONS
Differential Nonlinearity (DNL)
An ideal ADC exhibits code transitions that are exactly 1 LSB
apart. DNL is the deviation from this ideal value. Thus, every
code must have a finite width. No missing codes guaranteed to
12-bit resolution indicates that all 4096 codes, respectively,
must be present over all operating conditions.
Peak Nonlinearity
Peak nonlinearity, a full signal chain specification, refers to the
peak deviation of the output of the AD9821 from a true straight
line. The point used as “zero scale” occurs 1/2 LSB before the
first code transition. “Positive full scale” is defined as a Level 1,
1/2 LSB beyond the last code transition. The deviation is mea-
sured from the middle of each particular output code to the true
straight line. The error is then expressed as a percentage of the
2 V ADC full-scale signal. The input signal is always appropriately
gained up to fill the ADC’s full-scale range.
Total Output Noise
The rms output noise is measured using histogram techniques.
The standard deviation of the ADC output codes is calculated
in LSB and represents the rms noise level of the total signal
chain at the specified gain setting. The output noise can be
converted to an equivalent voltage using the relationship 1 LSB =
(ADC Full Scale/2
N
codes) when N is the bit resolution of the ADC.
For the AD9821, 1 LSB is 500
μ
V.
Power Supply Rejection (PSR)
The PSR is measured with a step change applied to the supply
pins. This represents a very high frequency disturbance on the
AD9821’s power supply. The PSR specification is calculated
from the change in the data outputs for a given step change in
the supply voltage.
Internal Delay for SHA
The internal delay (also called aperture delay) is the time delay
that occurs from when the sampling edge is applied to the AD9821
until the actual sample of the input signal is held. The DATACLK
samples the input signal during the transition from low to high,
so the internal delay is measured from each clock’s rising edge
to the instant the actual internal sample is taken.
EQUIVALENT INPUT CIRCUITS
330
DVDD
DVSS
Figure 1. Digital Inputs— DATACLK, CLPOB, PBLK, SCK, SL
DVDD
DVSS
DRVSS
DRVDD
THREE-
STATE
DATA
DOUT
Figure 2. Data Outputs—D0–D11
AVDD
ACVSS
ACVSS
60
Figure 3. VIN+ and VIN– (Pins 30 and 31)
330
DVDD
DVSS
DVDD
DVSS
DVSS
DATA IN
RNW
DATA OUT
Figure 4. SDATA (Pin 47)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD9822 | Complete 14-Bit CCD/CIS Signal Processor |
| AD9822JR | Complete 14-Bit CCD/CIS Signal Processor |
| AD9822JRS | Complete 14-Bit CCD/CIS Signal Processor |
| AD9823 | Correlated Double Sampler (CDS) |
| AD9823BRUZ | Correlated Double Sampler (CDS) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9821KSTRL | 制造商:Analog Devices 功能描述:AFE Video 1ADC 12-Bit 3.3V 48-Pin LQFP T/R 制造商:Rochester Electronics LLC 功能描述:12 BIT 40 MSPS IMAGING SIGNAL PROCESSOR - Tape and Reel |
| AD9821KSTZ | 制造商:Analog Devices 功能描述:AFE Video 1ADC 12-Bit 3.3V 48-Pin LQFP |
| AD9821KSTZRL | 制造商:Analog Devices 功能描述:AFE Video 1ADC 12-Bit 3.3V 48-Pin LQFP T/R |
| AD9821KSTZRL7 | 制造商:Analog Devices 功能描述:AFE Video 1ADC 12-Bit 3.3V 48-Pin LQFP T/R 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| AD9822 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Complete 14-Bit CCD/CIS Signal Processor |
發(fā)布緊急采購，3分鐘左右您將得到回復。