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參數(shù)資料
| 型號： | AD9821 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Complete 12-Bit 40 MSPS Imaging Signal Processor |
| 中文描述： | 完整的12位40 MSPS的影像信號處理器 |
| 文件頁數(shù)： | 9/16頁 |
| 文件大小： | 277K |
| 代理商： | AD9821 |
REV. 0
AD9821
–9–
INTERNAL REGISTER MAP AND SERIAL INTERFACE TIMING
Table I. Internal Register Map
Register
Name
Address
A0 A1 A2
Data Bits
D4
D0 D1 D2
D3
D5
D6
D7
D8
D9
D10
Operation
0 0 0
Input Mode
Selection
Power-Down
Modes
Software
Reset
OB Clamp
On/Off
0
1
1
2
0
1
0
1
0
1
VGA Gain
1 0 0
LSB
MSB
X
Clamp Level
0 1 0
LSB
MSB
X
X
X
Control
1 1 0
0
1
0
1
0
1
0
1
0
1
Clock Polarity Select for
CLP/DATA
0
1
0
1
0
1
X
NOTES
1
Internal use only. Must be set to 0.
2
Must be set to 1.
SDATA
SCK
SL
RNW
TEST BIT
0
A2
0
A0
A1
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
t
DS
NOTES:
1. SDATA BITS ARE INTERNALLY LATCHED ON THE RISING EDGES OF SCK.
2. RNW = READ-NOT WRITE. SET LOW FOR WRITE OPERATION.
3. TEST BITS = INTERNAL USE ONLY. MUST BE SET LOW.
4. SYSTEM UPDATE OF LOADED REGISTERS OCCURS ON SL RISING EDGE.
t
DH
t
LS
t
LH
Figure 7. Serial Write Operation
SDATA
SCK
SL
RNW
TEST BIT
1
0
0
A0
A1
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
t
DS
t
DH
t
LS
t
LH
NOTES:
1. RNW = READ-NOT WRITE. SET HIGH FOR READ OPERATION.
2. TEST BITS = INTERNAL USE ONLY. MUST BE SET LOW.
3. SERIAL DATA FROM THE SELECTED REGISTER IS VALID STARTING AFTER THE FIFTH SCK FALLING EDGE, AND IS UPDATED ON
SCK FALLING EDGES.
t
DV
Figure 8. Serial Readback Operation
SDATA
SCK
SL
A0 A1
A2
D0
D2
D3
D10 D0
D3
D2
RNW
0
0
D9
0
0
0
D0
1
2
9
20
19
17
16
8
6
5
4
3
26
27
30
38
37
35
34
29
44
...
...
...
...
10 BITS
VGA GAIN
D2
D3
D7
D0
D3
D2
D9
...
...
...
...
...
NOTES:
1. ANY NUMBER OF ADJACENT REGISTERS MAY BE LOADED SEQUENTIALLY, BEGINNING WITH THE LOWEST ADDRESS AND INCREMENTING ONE ADDRESS AT A TIME.
2. WHEN SEQUENTIALLY LOADING MULTIPLE REGISTERS, THE EXACT REGISTER LENGTH (SHOWN ABOVE) MUST BE USED FOR EACH REGISTER.
3. ALL LOADED REGISTERS WILL BE SIMULTANEOUSLY UPDATED WITH THE RISING EDGE OF SL.
8 BITS
CLAMP LEVEL
10 BITS
CONTROL
11 BITS
OPERATION
D1
D1
D1
D1
7
18
28
36
Figure 9. Continuous Serial Write Operation to All Registers
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