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參數(shù)資料
| 型號(hào)： | AD9816JS-80010 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類(lèi)： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Complete 12-Bit 6 MSPS CCD/CIS Signal Processor |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PQFP44 |
| 封裝： | PLASTIC, MQFP-44 |
| 文件頁(yè)數(shù)： | 11/16頁(yè) |
| 文件大?。?/td> | 171K |
| 代理商： | AD9816JS-80010 |
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AD9816
–11–
REV. A
CIRCUIT DESCRIPTIONS
Analog Input Configuration for CDS and SHA Mode
CDS Mode Operation
Figure 13 shows the equivalent input circuit for the CDS mode
of operation. The CCD signal is connected to the AD9816’s
analog inputs through a coupling capacitor C
IN
. The CCD
reference level is clamped during the CDSCLK1 pulse, when
the clamp switch closes and connects the externally-generated
3 V bias to the analog input. After the clamp switch opens
(CDSCLK1 low), the CCD data level will be level shifted by
the voltage held across C
IN
, and the SHA will sample the input
signal when the CDSCLK2 pulse goes low (see Figures 1 and 3
for CDS mode timing). In this sampling technique, the CDS
function is effectively performed across the input capacitor, C
IN
.
This CDS method has two additional considerations. First, the
CCD signal cannot be dc-coupled into the AD9816, because
the input capacitor is required. Second, the input clamp of the
AD9816 is operating as a pixel clamp, and must be asserted on
every pixel for true CDS operation. If line clamp operation is
desired, CDSCLK1 may be used at the start of each line to set
the proper dc voltage on C
IN
. Then, during the effective pixels
of each line, CDSCLK1 can be held low while CDSCLK2
samples the data levels of each pixel. Figure 5 shows the timing
for line clamp operation.
11
SHA
BUFFER
VING
I
BIAS
C
STRAY
CLAMP
SWITCH
16
3V
OFFSET
1.0k
V
1.5k
V
+5V
0.1
m
F
1
m
F
17
18
AD9816
C
IN
R
S
CCD SIGNAL
CDSCLK1
CDSCLK2
Figure 13. CDS Mode Input Circuit (All Channels Identical)
Input Signal Range for CDS Mode
An input dc bias level of 3 V allows a maximum 3 V p-p signal
swing from the CCD. Figure 14 shows a typical full-scale input
waveform to the AD9816, illustrating the allowable input range.
With a reference level of 3 V, the AD9816 can tolerate up to
2 V of reset feedthrough above the reference level. The inputs
of the AD9816 can also handle an input signal down to
AVSS – 0.3 V without any saturation recovery issues. Although
an input level below zero volts will be clipped to the ADC’s full-
scale output code, the input stage can respond quickly enough
to accurately process the next pixel that falls into the linear
input range. Any signals below AVSS – 0.3 V will turn on the
input protection diodes, and recovery from the saturated condi-
tion may take up to several milliseconds.
Input Capacitor C
IN
The recommended value for C
IN
is 1200 pF. This value has
been selected to provide the best overall performance when
considering three factors: input attenuation, linearity and signal
droop. The value of C
IN
may be optimized for a particular ap-
plication if these three factors are understood.
1. Attenuation (Gain Error)
The input voltage will be attenuated by the interaction of
C
IN
and C
STRAY
. C
STRAY
is less than 10 pF, which results in
an attenuation of about 0.8% when C
IN
is 1200 pF. The gain
error will increase accordingly as the value of C
IN
is decreased.
2. Linearity
The input capacitance of the AD9816 is shown in Figure 8
as C
STRAY
. A small portion of this capacitance is junction
capacitance, which will vary nonlinearly as the input voltage
to the AD9816 changes. When the input voltage is attenu-
ated by the combination of C
IN
and C
STRAY
, there will be a
small nonlinear component caused by the input junction
capacitance. The magnitude of the junction capacitance will
cause a 1 LSB (0.024%) nonlinearity over the 3 V input
range when a 1200 pF C
IN
is used. This nonlinearity will
increase if a smaller C
IN
is used.
3. Droop
The input bias current of the AD9816 is typically 10 nA and
is constant regardless of the AD9816’s input voltage. The
droop of the voltage across C
IN
can be calculated with the
following equation:
dV
=
i
BIAS
C
IN
×
(
t
)
where
t
is the time between clamp intervals. Between the
adjacent pixels of a scanned line, this droop will be insignifi-
cant. Between scanned lines, a 1 ms delay will produce a
droop of about 10 mV, which can be easily clamped on the
first pixel of the next line. If the value of C
IN
is reduced, the
droop will increase accordingly.
5V MAX RESET FEEDTHROUGH
3V REFERENCE LEVEL
(SET BY INPUT CLAMP)
0V MAX DATA LEVEL
–0.3V MAX SATURATED DATA LEVEL
MAX PEAK-PEAK SIGNAL
Figure 14. CCD Input Signal Clamped to 3 V
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD9816 | Complete 12-Bit 6 MSPS CCD/CIS Signal Processor(12位的采樣速率為6MSPS的CCD/CIS信號(hào)處理器) |
| AD9821 | Complete 12-Bit 40 MSPS Imaging Signal Processor |
| AD9821KST | Complete 12-Bit 40 MSPS Imaging Signal Processor |
| AD9822 | Complete 14-Bit CCD/CIS Signal Processor |
| AD9822JR | Complete 14-Bit CCD/CIS Signal Processor |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9816JSRL | 制造商:Rochester Electronics LLC 功能描述:- Tape and Reel 制造商:Analog Devices 功能描述: |
| AD9821 | 制造商:AD 制造商全稱(chēng):Analog Devices 功能描述:Complete 12-Bit 40 MSPS Imaging Signal Processor |
| AD9821KST | 制造商:Analog Devices 功能描述:AFE Video 1ADC 12-Bit 3.3V 48-Pin LQFP 制造商:Rochester Electronics LLC 功能描述:12 BIT 40 MSPS IMAGING SIGNAL PROCESSOR - Bulk |
| AD9821KSTRL | 制造商:Analog Devices 功能描述:AFE Video 1ADC 12-Bit 3.3V 48-Pin LQFP T/R 制造商:Rochester Electronics LLC 功能描述:12 BIT 40 MSPS IMAGING SIGNAL PROCESSOR - Tape and Reel |
| AD9821KSTZ | 制造商:Analog Devices 功能描述:AFE Video 1ADC 12-Bit 3.3V 48-Pin LQFP |
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