參數(shù)資料
型號： AD9806KST
廠商： ANALOG DEVICES INC
元件分類： 消費(fèi)家電
英文描述： Complete 10-Bit 18 MSPS CCD Signal Processor
中文描述： SPECIALTY CONSUMER CIRCUIT, PQFP48
封裝： PLASTIC, LQFP-48
文件頁數(shù)： 7/12頁
文件大?。?/td> 134K
代理商： AD9806KST
REV. 0
AD9806
–7–
TIMING SPECIFICATIONS
N
N+1
N+2
N+3
N+4
t
INHIBIT
t
ID
t
ID
t
OD
t
HOLD
ADCCLK RISING EDGE PLACEMENT
N
–
0
N
–
9
N
–
8
N
–
7
N
–
6
N
–
5
CCD
SHP
SHD
ADCCLK
D0
–
D9
NOTES:
1. SHP AND SHD SHOULD BE OPTIMALLY ALIGNED WITH THE CCD SIGNAL. SAMPLES ARE TAKEN AT THE RISING EDGES.
2. ADCCLK RISING EDGE MUST OCCUR AT LEAST 15ns AFTER THE RISING EDGE OF SHP (
t
).
3. RECOMMENDED PLACEMENT FOR ADCCLK RISING EDGE IS BETWEEN THE RISING EDGE OF SHD AND FALLING EDGE OF SHP.
4. OUTPUT LATENCY IS 9 CYCLES.
5. ACTIVE LOW CLOCK PULSE MODE IS SHOWN.
Figure 1. CCD-MODE Timing
t
ID
t
OD
t
HOLD
N
N+1
N+2
N+3
N+4
N
–
9
N
–
8
N
–
7
N+5
VIDEO
INPUT
ADCCLK
D0
–
D9
N
–
6
N
–
5
NOTE:
EXAMPLE OF OUTPUT DATA LATCHED BY ADCCLK RISING EDGE.
Figure 2. AUX-, AUXMID-, ADC-Mode Timing
CCD
SIGNAL
CLPOB
CLPDM
PBLK
EFFECTIVE
PIXELS
OPTICAL BLACK
BLANKING
INTERVAL
DUMMY BLACK
EFFECTIVE
PIXELS
NOTES:
1. CLPOB PULSEWIDTH SHOULD BE A MINIMUM OF 10 OB PIXELS WIDE, 20 OB PIXELS ARE RECOMMENDED.
2. CLPDM PULSEWIDTH SHOULD BE AT LEAST 1 s WIDE.
3. PBLK IS NOT REQUIRED, BUT RECOMMENDED IF THE CCD SIGNAL AMPLITUDE EXCEEDS 1V p-p.
4. CLPDM OVERWRITES PBLK.
5. ACTIVE LOW CLAMP PULSE MODE IS SHOWN.
Figure 3. CCD-MODE Clamp Timing
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